[U-Boot] [EXT] [PATCH 2/2] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*

[Vignesh Raghavendra]

Hi Ashish,

On 23/09/19 2:37 PM, Ashish Kumar wrote:
> 
[...]
>> Lets see if something stands out.
> Hi Vignesh, Eugeniy,
> 
> Could you please provide me dump for n25q512a which consists of all 6 JEDEC id bytes.
> I had initiated mail chain with MICRON FAE, and they suggest that extended id may be different for
> n25q512a  from mt25qu512a.
> 
> I have dumped JEDEC ID from mt25qu512a "20, bb, 20, 10, 44, 00" , the second last byte is supposed to be different as per FAE.
> 
> Bit 6 
> device
> Generation
> 1 = 2nd
> generation
> 

Thats great! Thanks for getting that information!

>From Eugeniy's debug dumps in other mail chain, I see JEDEC ID of that flash is:
 " 20 ba 20 10 00 00" (does not support 4 byte addressing opcodes)

So these variants can be differentiated quite easily. I will send out a series fixing those entries.

Regards
Vignesh

> Regards
> Ashish 
>>
>> Regards
>> Vignesh
>>
>>> Still, so we have such an op-in possibility to enable 4 byte opcodes
>>> on these chips?
>>>
>>> Regards,
>>> Simon
>>>
>>>
>>>     Regards
>>>     Ashish
>>>     >
>>>     > Signed-off-by: Vignesh Raghavendra <vigneshr at ti.com
>>>     <mailto:vigneshr at ti.com>> For n25q512ax3:
>>>     > Tested-by: Eugeniy Paltsev <paltsev at synopsys.com
>>>     <mailto:paltsev at synopsys.com>>
>>>     > ---
>>>     >  drivers/mtd/spi/spi-nor-ids.c | 6 +++---
>>>     >  1 file changed, 3 insertions(+), 3 deletions(-)
>>>     >
>>>     > diff --git a/drivers/mtd/spi/spi-nor-ids.c
>>>     b/drivers/mtd/spi/spi-nor-ids.c
>>>     > index f32a6c7d464b..5a7fe07c8309 100644
>>>     > --- a/drivers/mtd/spi/spi-nor-ids.c
>>>     > +++ b/drivers/mtd/spi/spi-nor-ids.c
>>>     > @@ -161,10 +161,10 @@ const struct flash_info spi_nor_ids[] = {
>>>     >         { INFO("n25q064a",    0x20bb17, 0, 64 * 1024,  128, SECT_4K |
>>>     > SPI_NOR_QUAD_READ) },
>>>     >         { INFO("n25q128a11",  0x20bb18, 0, 64 * 1024,  256, SECT_4K |
>>>     > SPI_NOR_QUAD_READ) },
>>>     >         { INFO("n25q128a13",  0x20ba18, 0, 64 * 1024,  256, SECT_4K |
>>>     > SPI_NOR_QUAD_READ) },
>>>     > -       { INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K |
>>>     > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> SPI_NOR_4B_OPCODES) },
>>>     > +       { INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K |
>>>     > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>>>     >         { INFO("n25q256ax1",  0x20bb19, 0, 64 * 1024,  512, SECT_4K |
>>>     > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>>>     > -       { INFO("mt25qu512a (n25q512a)",    0x20bb20, 0, 64 * 1024,
>>>     1024,
>>>     > SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
>> SPI_NOR_4B_OPCODES) },
>>>     > -       { INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024,
>>>     SECT_4K | USE_FSR |
>>>     > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>>>     > +       { INFO("mt25qu512a (n25q512a)",    0x20bb20, 0, 64 * 1024,
>>>     1024,
>>>     > SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
>>>     > +       { INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024, SECT_4K |
>>>     > + USE_FSR | SPI_NOR_QUAD_READ) },
>>>     >         { INFO("n25q00",      0x20ba21, 0, 64 * 1024, 2048,
>>>     SECT_4K | USE_FSR |
>>>     > SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>>>     >         { INFO("n25q00a",     0x20bb21, 0, 64 * 1024, 2048,
>>>     SECT_4K | USE_FSR |
>>>     > SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>>>     >         { INFO("mt25qu02g",   0x20bb22, 0, 64 * 1024, 4096,
>>>     SECT_4K | USE_FSR |
>>>     > SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>>>     > --
>>>     > 2.23.0
>>>
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>>
>> --
>> Regards
>> Vignesh

-- 
Regards
Vignesh