[U-Boot] [EXT] [PATCH 2/2] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*

[Tudor.Ambarus at microchip.com]

Hi, Simon,

On 09/23/2019 12:30 PM, Simon Goldschmidt wrote:

cut

>>>     > Subject: [EXT] [PATCH 2/2] spi-nor: spi-nor-ids: Disable
>>>     > SPI_NOR_4B_OPCODES for n25q512* and n25q256*
>>>     >
>>>     > Caution: EXT Email
>>>     >
>>>     > Not all variants of n25q256* and n25q512* support 4 Byte stateless
>>>     > addressing opcodes and there is no easy way to discover at runtime
>>>     whether
>>>     > the flash supports this feature or not.
>>>     > Therefore don't set SPI_NOR_4B_OPCODES for these flashes.
>>>     Hi Vignesh,
>>>
>>>     I think it will be good to keep it here and disable this for boards
>>>     by using not set flag in config
>>>     Like
>>>     # SPI_NOR_4B_OPCODES is not set
>>>
>>
>> SPI_NOR_4B_OPCODES is not a config option. Are you suggesting to add
>> one? config options don't scale well especially when same defconfig is
>> used for multiple boards that potentially have different flashes
>>
>>>
>>> I'd prefer to take this patch, as this is what Linux does.
>>
>> No, this is not what Linux does. There is no opt-in or opt-out option.
>> Decision to use 4 byte opcode is done at runtime based on flash that's
>> detected. Either based on info->flags for that part or by parsing SFDP
>> table. There is no config option of DT option to force 4 byte addressing
>>
>>> I think it's better to have an opt-in option. That way, all chips work with the
>>> default settings (even if that means some chips don't use 4 baste
>>> opcodes even if they could).
>>>
>>
>> One solution would be to look at SFDP tables of two variants of flash
>> and see if there are any differences that can be used as a clue.
>>
>> Simon,
>> Could you provide dump of SFDP tables and all the 6 bytes READ ID of the
>> flash that you have?
> 
> I have a n251256a with JEDEC ID 20, ba, 19, 10, 44, 00.

Is this a n25q256a or a MT25QL256ABA? We want to check if there are n25q256a
flashes that have the 6th bit of the Extended Device Id set to one or not.
According to n25q256a datasheet the bit 6 is reserved (which probably translates
to being zero), while on MT25QL256ABA is set to one.

Cheers,
ta