[U-Boot] [PATCH RFT 3/3] spi-nor: spi-nor-ids: Add entries for newer variants of n25q256* and n25q512*

[Simon Goldschmidt]

+Tudor Ambarus (from discussion in https://patchwork.ozlabs.org/patch/1160501/)

On Tue, Sep 24, 2019 at 1:47 PM Simon Goldschmidt
<simon.k.r.goldschmidt at gmail.com> wrote:
>
> On Tue, Sep 24, 2019 at 7:55 AM Vignesh Raghavendra <vigneshr at ti.com> wrote:
> >
> > Newer variants of n25q256* and n25q512* flashes support 4 Byte
> > addressing opcodes. Add entries for the same. These flashes Bit 6 set in
> > 5th byte of READ ID response.
> >
> > Signed-off-by: Vignesh Raghavendra <vigneshr at ti.com>
> > ---
> >  drivers/mtd/spi/spi-nor-ids.c | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> > index 967537eafb55..0074073b123a 100644
> > --- a/drivers/mtd/spi/spi-nor-ids.c
> > +++ b/drivers/mtd/spi/spi-nor-ids.c
> > @@ -161,11 +161,14 @@ const struct flash_info spi_nor_ids[] = {
> >         { INFO("n25q064a",    0x20bb17, 0, 64 * 1024,  128, SECT_4K | SPI_NOR_QUAD_READ) },
> >         { INFO("n25q128a11",  0x20bb18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
> >         { INFO("n25q128a13",  0x20ba18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
> > +       { INFO6("n25q256a",    0x20ba19, 0x104400, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>
> From the discussion in the other thread, this should probably be named
> "mt25-something"? Seems like the 0x44 in the 5th byte wouldn't be found in the
> n25q256a?
>
> Regards,
> Simon
>
> >         { INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > +       { INFO6("n25q256ax1",  0x20bb19, 0x104400, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> >         { INFO("n25q256ax1",  0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },
> >         { INFO6("mt25qu512a (n25q512a)",  0x20bb20, 0x104400, 64 * 1024, 1024,
> >                  SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> >         { INFO("n25q512a",    0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
> > +       { INFO6("n25q512ax3",  0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> >         { INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
> >         { INFO("n25q00",      0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> >         { INFO("n25q00a",     0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> > --
> > 2.23.0
> >