[U-Boot] [EXT] [PATCH 2/2] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*

Vignesh Raghavendra vigneshr at ti.com
Tue Sep 24 11:53:59 UTC 2019


On 24-Sep-19 5:15 PM, Simon Goldschmidt wrote:
> Hi Tudor,
> On Tue, Sep 24, 2019 at 1:36 PM <Tudor.Ambarus at microchip.com> wrote:

>>>> Simon,
>>>> Could you provide dump of SFDP tables and all the 6 bytes READ ID of the
>>>> flash that you have?
>>> I have a n251256a with JEDEC ID 20, ba, 19, 10, 44, 00.
>> Is this a n25q256a or a MT25QL256ABA? We want to check if there are n25q256a
>> flashes that have the 6th bit of the Extended Device Id set to one or not.
>> According to n25q256a datasheet the bit 6 is reserved (which probably translates
>> to being zero), while on MT25QL256ABA is set to one.
> Right, this really is a MT25QL256ABA, I guess. I'm not quite familiar with the
> print on the housing, sorry. We had both and here, it's probably the MT, not
> the nq.

But, do you have access to n25q variants? And does that support 4 Byte
addressing opcode? What does its JEDEC ID read?

> I also wasn't really aware of the differences between those two, sorry.
> Regards,
> Simon
>> Cheers,
>> ta

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