[U-Boot] [PATCH] LS1043A: Add bugfix for IFC beyond 4 GiB

[georg.kirschbaum at siemens.com]

>From b5691db49dc3844b650f78634c35f091df906095 Mon Sep 17 00:00:00 2001
From: Georg Kirschbaum <georg.kirschbaum at siemens.com>
Date: Fri, 13 Sep 2019 14:45:30 +0200
Subject: [PATCH] LS1043A: Add bugfix for IFC beyond 4 GiB

IFC region 2 [0x620000000, 0x700000000) was not
usable because the MMU entries were missing.
In case of CONFIG_FSL_LSCH2 they are added in
early_map and final_map.

Signed-off-by: Georg Kirschbaum <georg.kirschbaum at siemens.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c        | 12 ++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  2 ++
 2 files changed, 14 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-
layerscape/cpu.c
index edb9c96658..4ecdb6a7c4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -168,6 +168,12 @@ static struct mm_region early_map[] = {
 #endif
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
+#ifdef CONFIG_FSL_IFC
+	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+	  CONFIG_SYS_FSL_IFC_SIZE2,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+	},
+#endif
 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 	  CONFIG_SYS_FSL_DRAM_SIZE2,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN 
|
@@ -343,6 +349,12 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
+#ifdef CONFIG_FSL_IFC
+	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+	  CONFIG_SYS_FSL_IFC_SIZE2,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+	},
+#endif
 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 	  CONFIG_SYS_FSL_DRAM_SIZE2,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/
include/asm/arch-fsl-layerscape/cpu.h
index 7759acdb8f..aa48b3bd45 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -83,6 +83,8 @@
 #define CONFIG_SYS_FSL_DRAM_SIZE1	0x80000000
 #define CONFIG_SYS_FSL_QBMAN_BASE	0x500000000
 #define CONFIG_SYS_FSL_QBMAN_SIZE	0x10000000
+#define CONFIG_SYS_FSL_IFC_BASE2	0x620000000
+#define CONFIG_SYS_FSL_IFC_SIZE2	0xE0000000	/* 3.5GB */
 #define CONFIG_SYS_FSL_DRAM_BASE2	0x880000000
 #define CONFIG_SYS_FSL_DRAM_SIZE2	0x780000000	/* 30GB */
 #define CONFIG_SYS_PCIE1_PHYS_SIZE	0x800000000
-- 
2.23.0