[PATCH v1 1/1] phy: add support for stingray PAXB PHY controller
Stefan Roese
sr at denx.de
Thu Apr 2 09:50:12 CEST 2020
On 02.04.20 09:17, Rayagonda Kokatanur wrote:
> On Thu, Apr 2, 2020 at 12:05 PM Stefan Roese <sr at denx.de> wrote:
>>
>> On 02.04.20 06:36, Rayagonda Kokatanur wrote:
>>> From: Srinath Mannam <srinath.mannam at broadcom.com>
>>>
>>> Add support for stingray PAXB PHY controller driver.
>>> This driver supports maximum 8 PAXB phys using pipemux data.
>>>
>>> Signed-off-by: Srinath Mannam <srinath.mannam at broadcom.com>
>>> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur at broadcom.com>
>>> ---
>>> drivers/phy/Kconfig | 7 ++
>>> drivers/phy/Makefile | 1 +
>>> drivers/phy/phy-bcm-sr-pcie.c | 180 ++++++++++++++++++++++++++++++++++
>>> 3 files changed, 188 insertions(+)
>>> create mode 100644 drivers/phy/phy-bcm-sr-pcie.c
>>>
>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>>> index a72f34f0d4..f7003807fc 100644
>>> --- a/drivers/phy/Kconfig
>>> +++ b/drivers/phy/Kconfig
>>> @@ -84,6 +84,13 @@ config BCM6368_USBH_PHY
>>> help
>>> Support for the Broadcom MIPS BCM6368 USBH PHY.
>>>
>>> +config BCM_SR_PCIE_PHY
>>> + bool "Broadcom Stingray PCIe PHY driver"
>>> + depends on PHY
>>> + help
>>> + Enable this to support the Broadcom Stingray PCIe PHY
>>> + If unsure, say N.
>>> +
>>> config PHY_DA8XX_USB
>>> tristate "TI DA8xx USB PHY Driver"
>>> depends on PHY && ARCH_DAVINCI
>>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>>> index 43ce62e08c..3958f7899c 100644
>>> --- a/drivers/phy/Makefile
>>> +++ b/drivers/phy/Makefile
>>> @@ -9,6 +9,7 @@ obj-$(CONFIG_BCM6318_USBH_PHY) += bcm6318-usbh-phy.o
>>> obj-$(CONFIG_BCM6348_USBH_PHY) += bcm6348-usbh-phy.o
>>> obj-$(CONFIG_BCM6358_USBH_PHY) += bcm6358-usbh-phy.o
>>> obj-$(CONFIG_BCM6368_USBH_PHY) += bcm6368-usbh-phy.o
>>> +obj-$(CONFIG_BCM_SR_PCIE_PHY) += phy-bcm-sr-pcie.o
>>> obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
>>> obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
>>> obj-$(CONFIG_AM654_PHY) += phy-ti-am654.o
>>> diff --git a/drivers/phy/phy-bcm-sr-pcie.c b/drivers/phy/phy-bcm-sr-pcie.c
>>> new file mode 100644
>>> index 0000000000..6c932f6478
>>> --- /dev/null
>>> +++ b/drivers/phy/phy-bcm-sr-pcie.c
>>> @@ -0,0 +1,180 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (C) 2019 Broadcom
>>> + */
>>> +
>>> +#include <asm/io.h>
>>> +#include <common.h>
>>> +#include <dm.h>
>>> +#include <dm/device.h>
>>> +#include <generic-phy.h>
>>> +
>>> +/* we have up to 8 PAXB based RC. The 9th one is always PAXC */
>>> +#define SR_NR_PCIE_PHYS 8
>>> +
>>> +#define PCIE_PIPEMUX_CFG_OFFSET 0x10c
>>> +#define PCIE_PIPEMUX_SELECT_STRAP 0xf
>>> +
>>> +#define CDRU_STRAP_DATA_LSW_OFFSET 0x5c
>>> +#define PCIE_PIPEMUX_SHIFT 19
>>> +#define PCIE_PIPEMUX_MASK 0xf
>>
>> Please use GENMASK() etc from bitops.h
>
> Do you mean this ?
> #define PCIE_PIPEMUX_MASK GENMASK(3, 0)
Ye, and _SELECT_STRAP. And I first thought that you could remove the
SHIFT macro above but it seems that the value is used in different bit
positions in both registers.
>>
>>> +
>>> +struct sr_pcie_phy_core;
>>
>> You should be able to drop this line, the struct is defined
>> directly below...
>
> okay, thank you.
>
>>
>>> +
>>> +/**
>>> + * struct sr_pcie_phy_core - Stingray PCIe PHY core control
>>> + *
>>> + * @dev: pointer to device
>>> + * @base: base register of PCIe SS
>>> + * @cdru: CDRU base address
>>> + * @pipemux: pipemuex strap
>>> + */
>>> +struct sr_pcie_phy_core {
>>> + struct udevice *dev;
>>> + void __iomem *base;
>>> + void __iomem *cdru;
>>> + u32 pipemux;
>>> +};
>>> +
>>> +/*
>>> + * PCIe PIPEMUX lookup table
>>> + *
>>> + * Each array index represents a PIPEMUX strap setting
>>> + * The array element represents a bitmap where a set bit means the PCIe
>>> + * core and associated serdes has been enabled as RC and is available for use
>>> + */
>>> +static const u8 pipemux_table[] = {
>>> + /* PIPEMUX = 0, EP 1x16 */
>>> + 0x00,
>>> + /* PIPEMUX = 1, EP 1x8 + RC 1x8, core 7 */
>>> + 0x80,
>>> + /* PIPEMUX = 2, EP 4x4 */
>>> + 0x00,
>>> + /* PIPEMUX = 3, RC 2x8, cores 0, 7 */
>>> + 0x81,
>>> + /* PIPEMUX = 4, RC 4x4, cores 0, 1, 6, 7 */
>>> + 0xc3,
>>> + /* PIPEMUX = 5, RC 8x2, all 8 cores */
>>> + 0xff,
>>> + /* PIPEMUX = 6, RC 3x4 + 2x2, cores 0, 2, 3, 6, 7 */
>>> + 0xcd,
>>> + /* PIPEMUX = 7, RC 1x4 + 6x2, cores 0, 2, 3, 4, 5, 6, 7 */
>>> + 0xfd,
>>> + /* PIPEMUX = 8, EP 1x8 + RC 4x2, cores 4, 5, 6, 7 */
>>> + 0xf0,
>>> + /* PIPEMUX = 9, EP 1x8 + RC 2x4, cores 6, 7 */
>>> + 0xc0,
>>> + /* PIPEMUX = 10, EP 2x4 + RC 2x4, cores 1, 6 */
>>> + 0x42,
>>> + /* PIPEMUX = 11, EP 2x4 + RC 4x2, cores 2, 3, 4, 5 */
>>> + 0x3c,
>>> + /* PIPEMUX = 12, EP 1x4 + RC 6x2, cores 2, 3, 4, 5, 6, 7 */
>>> + 0xfc,
>>> + /* PIPEMUX = 13, RC 2x4 + RC 1x4 + 2x2, cores 2, 3, 6 */
>>> + 0x4c,
>>> +};
>>> +
>>> +/*
>>> + * Return true if the strap setting is valid
>>> + */
>>> +static bool pipemux_strap_is_valid(u32 pipemux)
>>> +{
>>> + return !!(pipemux < ARRAY_SIZE(pipemux_table));
>>> +}
>>> +
>>> +/*
>>> + * Read the PCIe PIPEMUX from strap
>>> + */
>>> +static u32 pipemux_strap_read(struct sr_pcie_phy_core *core)
>>> +{
>>> + u32 pipemux;
>>> +
>>> + /*
>>> + * Read PIPEMUX configuration register to determine the pipemux setting
>>> + *
>>> + * In the case when the value indicates using HW strap, fall back to
>>> + * use HW strap
>>> + */
>>> + pipemux = readl(core->base + PCIE_PIPEMUX_CFG_OFFSET);
>>> + pipemux &= PCIE_PIPEMUX_MASK;
>>> + if (pipemux == PCIE_PIPEMUX_SELECT_STRAP) {
>>> + pipemux = readl(core->cdru + CDRU_STRAP_DATA_LSW_OFFSET);
>>> + pipemux >>= PCIE_PIPEMUX_SHIFT;
>>> + pipemux &= PCIE_PIPEMUX_MASK;
>>> + }
>>> +
>>> + return pipemux;
>>> +}
>>> +
>>> +static int sr_pcie_phy_init(struct phy *phy)
>>> +{
>>> + struct sr_pcie_phy_core *core = dev_get_priv(phy->dev);
>>> + unsigned int core_idx = phy->id;
>>> +
>>> + debug("%s %lx\n", __func__, phy->id);
>>> + /*
>>> + * Check whether this PHY is for root complex or not. If yes, return
>>> + * zero so the host driver can proceed to enumeration. If not, return
>>> + * an error and that will force the host driver to bail out
>>> + */
>>> + if (!!((pipemux_table[core->pipemux] >> core_idx) & 0x1))
>>> + return 0;
>>> +
>>> + return -ENODEV;
>>> +}
>>> +
>>> +static int sr_pcie_phy_xlate(struct phy *phy, struct ofnode_phandle_args *args)
>>> +{
>>> + debug("%s %d\n", __func__, args->args[0]);
>>> + if (args->args_count && args->args[0] < SR_NR_PCIE_PHYS)
>>> + phy->id = args->args[0];
>>> + else
>>> + return -ENODEV;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static const struct phy_ops sr_pcie_phy_ops = {
>>> + .of_xlate = sr_pcie_phy_xlate,
>>> + .init = sr_pcie_phy_init,
>>> +};
>>> +
>>> +static int sr_pcie_phy_probe(struct udevice *dev)
>>> +{
>>> + struct sr_pcie_phy_core *core = dev_get_priv(dev);
>>> +
>>> + core->dev = dev;
>>> +
>>> + core->base = (void __iomem *)devfdt_get_addr_name(dev, "reg_base");
>>> + core->cdru = (void __iomem *)devfdt_get_addr_name(dev, "cdru_base");
>>> + debug("ip base %p\n", core->base);
>>> + debug("cdru base %p\n", core->cdru);
>>> +
>>> + /* read the PCIe PIPEMUX strap setting */
>>> + core->pipemux = pipemux_strap_read(core);
>>> + if (!pipemux_strap_is_valid(core->pipemux)) {
>>> + pr_err("invalid PCIe PIPEMUX strap %u\n",
>>> + core->pipemux);
>>
>> Could this pr_err() fit into one line?
>
> okay, thank you.
>
>>
>>> + return -EIO;
>>> + }
>>> + debug("%s %#x\n", __func__, core->pipemux);
>>> +
>>> + pr_info("Stingray PCIe PHY driver initialized\n");
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static const struct udevice_id sr_pcie_phy_match_table[] = {
>>> + { .compatible = "brcm,sr-pcie-phy" },
>>> + { }
>>> +};
>>> +
>>> +U_BOOT_DRIVER(sr_pcie_phy) = {
>>> + .name = "sr-pcie-phy",
>>> + .id = UCLASS_PHY,
>>> + .probe = sr_pcie_phy_probe,
>>> + .of_match = sr_pcie_phy_match_table,
>>> + .ops = &sr_pcie_phy_ops,
>>> + .platdata_auto_alloc_size = sizeof(struct sr_pcie_phy_core),
>>> + .priv_auto_alloc_size = sizeof(struct sr_pcie_phy_core),
>>> +};
>>>
>>
>> Thanks,
>> Stefan
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