[PATCH v1 1/2] clk: socfpga: Read the clock parent's register base in probe function

[Simon Glass]

Hi Marek,

On Thu, 2 Apr 2020 at 13:45, Marek Vasut <marex at denx.de> wrote:
>
> On 4/2/20 8:50 PM, Simon Glass wrote:
> > Hi.
>
> Hi,
>
> [...]
>
> >>>>>>>> I suspect we could change this, so that
> >>>>>>>> device_ofdata_to_platdata() first calls itself on its parent.
> >>>>>>>>
> >>>>>>>> I can think of various reasons why this change might be desirable.
> >>>>>>>
> >>>>>>> I think this is how it worked before already.
> >>>>>>
> >>>>>> Well effectively, yes, because ofdata and probe were joined together.
> >>>>
> >>>>> Simon, do you have plan to fix this DM core issue ?
> >>>>
> >>>> I'm not sure it definitely should be changed. But I'll do a patch and
> >>>> see how it looks.
> >>>
> >>> Do I understand it correctly that the patch
> >>> 82de42fa14682d408da935adfb0f935354c5008f actually completely breaks
> >>> SoCFPGA ? Then I would say this is a release blocker ?
> >> Yes. A10 SPL won't boot at all. It crashes during the clock manager setup.
> >
> > This came in right at the beginning of the cycle. I thought the
> > purpose of the 3-month cycle was to allow time to test?
>
> It was ... altera ?
>
> > I do plan to try out changing the behaviour to read a parent's ofdata
> > before the child, but I am not comfortable adding such a major change
> > just before a release. It could have any number of ill effects.
> >
> > Can you update the clock driver? E.g. you could move some of the code
> > from socfpga_a10_ofdata_to_platdata() to a probe() method?
>
> Can we revert the patch which broke arria10 instead ? It did work
> before, so who knows how many other ill side effects there are ...

No, sorry, we need to fix Altera. Other boards have fixed driver bugs
exposed by the patch.

BTW what is a good Altera board to get that doesn't cost too much?

Regards,
Simon