[PATCH v1 1/2] clk: socfpga: Read the clock parent's register base in probe function

[Tom Rini]

On Thu, Apr 02, 2020 at 11:07:31PM +0200, Marek Vasut wrote:
> On 4/2/20 10:54 PM, Tom Rini wrote:
> [...]
> 
> >>>>>> I'm not sure it definitely should be changed. But I'll do a patch and
> >>>>>> see how it looks.
> >>>>>
> >>>>> Do I understand it correctly that the patch
> >>>>> 82de42fa14682d408da935adfb0f935354c5008f actually completely breaks
> >>>>> SoCFPGA ? Then I would say this is a release blocker ?
> >>>> Yes. A10 SPL won't boot at all. It crashes during the clock manager setup.
> >>>
> >>> This came in right at the beginning of the cycle. I thought the
> >>> purpose of the 3-month cycle was to allow time to test?
> >>
> >> It was ... altera ?
> > 
> > Sorry, I'm missing how that's an answer to the question.  This came in
> > basically right at the start of the merge window.
> 
> I don't have an A10 available right now, so what can I do ?

Ah, so the answer is "I can't test this platform myself".  That's what
then, thanks.

-- 
Tom
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