[PATCH 3/3] arm: caches: manage phys_addr_t overflow in mmu_set_region_dcache_behaviour

[Patrick Delaunay]

Detect and solve the overflow on phys_addr_t type for start + size in
mmu_set_region_dcache_behaviour() function.

This issue occurs for example with ARM32, start = 0xC0000000 and
size = 0x40000000: start + size = 0x100000000 and end = 0x0.

Overflow is detected when end < start.
In normal case the previous behavior is still used: when start is not
aligned on MMU section, the end address is only aligned after the sum
start + size.

Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com>
---

 arch/arm/lib/cache-cp15.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index d15144188b..e5a7fd0ef4 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -63,6 +63,11 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 
 	end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
 	start = start >> MMU_SECTION_SHIFT;
+
+	/* phys_addr_t overflow detected */
+	if (end < start)
+		end = (~(phys_addr_t)0x0 >> MMU_SECTION_SHIFT) + 1;
+
 #ifdef CONFIG_ARMV7_LPAE
 	debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
 	      option);
-- 
2.17.1