[PATCH v2 2/2] arm: stm32mp: activate data cache on DDR in SPL
Patrick Delaunay
patrick.delaunay at st.com
Fri Apr 3 11:25:37 CEST 2020
Activate cache on DDR to improves the accesses to DDR used by SPL:
- CONFIG_SPL_BSS_START_ADDR
- CONFIG_SYS_SPL_MALLOC_START
Cache is configured only when DDR is fully initialized,
to avoid speculative access and issue in get_ram_size().
Data cache is deactivated at the end of SPL, to flush the data cache
and the TLB.
Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com>
---
Changes in v2:
- new
arch/arm/mach-stm32mp/spl.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c
index 9cd7b418a4..279121af75 100644
--- a/arch/arm/mach-stm32mp/spl.c
+++ b/arch/arm/mach-stm32mp/spl.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <cpu_func.h>
#include <dm.h>
#include <hang.h>
#include <spl.h>
@@ -117,4 +118,24 @@ void board_init_f(ulong dummy)
printf("DRAM init failed: %d\n", ret);
hang();
}
+
+ /*
+ * activate cache on DDR only when DDR is fully initialized
+ * to avoid speculative access and issue in get_ram_size()
+ */
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
+ DCACHE_DEFAULT_OPTION);
+}
+
+void spl_board_prepare_for_boot(void)
+{
+ dcache_disable();
+ debug("SPL bye\n");
+}
+
+void spl_board_prepare_for_boot_linux(void)
+{
+ dcache_disable();
+ debug("SPL bye\n");
}
--
2.17.1
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