[PATCH] net: zynq-gem: Setup and use mdio base separately

[Michal Simek]

pá 6. 3. 2020 v 10:57 odesílatel Michal Simek <michal.simek at xilinx.com> napsal:
>
> Not all IPs have private MDIO bus and MDIO bus should be shared between
> several IPs. In past one patch tried to implement it
> (https://lists.denx.de/pipermail/u-boot/2018-February/319285.html)
> in pretty raw way but it is not the cleanest solution.
> This patch is just taking the part of that solution to be able to handle it
> over releases without conflicts.
>
> Signed-off-by: Michal Simek <michal.simek at xilinx.com>
> ---
>
>  drivers/net/zynq_gem.c | 16 ++++++++++------
>  1 file changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
> index bb9e4366f081..49388f8aec6f 100644
> --- a/drivers/net/zynq_gem.c
> +++ b/drivers/net/zynq_gem.c
> @@ -195,6 +195,7 @@ struct zynq_gem_priv {
>         int phyaddr;
>         int init;
>         struct zynq_gem_regs *iobase;
> +       struct zynq_gem_regs *mdiobase;
>         phy_interface_t interface;
>         struct phy_device *phydev;
>         ofnode phy_of_node;
> @@ -209,7 +210,7 @@ static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
>                         u32 op, u16 *data)
>  {
>         u32 mgtcr;
> -       struct zynq_gem_regs *regs = priv->iobase;
> +       struct zynq_gem_regs *regs = priv->mdiobase;
>         int err;
>
>         err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
> @@ -295,7 +296,7 @@ static int zynq_phy_init(struct udevice *dev)
>  {
>         int ret;
>         struct zynq_gem_priv *priv = dev_get_priv(dev);
> -       struct zynq_gem_regs *regs = priv->iobase;
> +       struct zynq_gem_regs *regs_mdio = priv->mdiobase;
>         const u32 supported = SUPPORTED_10baseT_Half |
>                         SUPPORTED_10baseT_Full |
>                         SUPPORTED_100baseT_Half |
> @@ -304,7 +305,7 @@ static int zynq_phy_init(struct udevice *dev)
>                         SUPPORTED_1000baseT_Full;
>
>         /* Enable only MDIO bus */
> -       writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
> +       writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs_mdio->nwctrl);
>
>         priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
>                                    priv->interface);
> @@ -333,6 +334,7 @@ static int zynq_gem_init(struct udevice *dev)
>         unsigned long clk_rate = 0;
>         struct zynq_gem_priv *priv = dev_get_priv(dev);
>         struct zynq_gem_regs *regs = priv->iobase;
> +       struct zynq_gem_regs *regs_mdio = priv->mdiobase;
>         struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
>         struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
>
> @@ -400,7 +402,7 @@ static int zynq_gem_init(struct udevice *dev)
>                 writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
>
>                 /* Setup for Network Control register, MDIO, Rx and Tx enable */
> -               setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
> +               setbits_le32(&regs_mdio->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
>
>                 /* Disable the second priority queue */
>                 dummy_tx_bd->addr = 0;
> @@ -741,6 +743,7 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
>
>         pdata->iobase = (phys_addr_t)dev_read_addr(dev);
>         priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
> +       priv->mdiobase = priv->iobase;
>         /* Hardcode for now */
>         priv->phyaddr = -1;
>
> @@ -766,8 +769,9 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
>
>         priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
>
> -       printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
> -              priv->phyaddr, phy_string_for_interface(priv->interface));
> +       printf("\nZYNQ GEM: %lx, mdio bus %lx, phyaddr %d, interface %s\n",
> +              (ulong)priv->iobase, (ulong)priv->mdiobase, priv->phyaddr,
> +              phy_string_for_interface(priv->interface));
>
>         return 0;
>  }
> --
> 2.25.1
>

Applied.
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs