[PATCH 1/6] net: dwc_eth_qos: Fully rewrite RX descriptor field 3

Patrick DELAUNAY patrick.delaunay at st.com
Tue Apr 7 11:49:09 CEST 2020

Dear Marek,

> From: Patrick DELAUNAY
> Sent: lundi 6 avril 2020 17:11
> Dear Marek,
> > From: Marek Vasut <marex at denx.de>
> > Sent: lundi 23 mars 2020 02:45
> >
> > The RX descriptor field 3 should contain only OWN and BUF1V bits
> > before being used for receiving data by the DMA engine. However, right
> > now, if the descriptor was already used for receiving data and is
> > being cleared, the field 3 is only modified and the aforementioned two
> > bits are ORRed into the field. This could lead to a residual dirty
> > bits being left in the field 3 from previous transfer, and it generally does. Fully
> set the field 3 instead to clear those residual dirty bits.
> >
> > Signed-off-by: Marek Vasut <marex at denx.de>
> > Cc: Joe Hershberger <joe.hershberger at ni.com>
> > Cc: Patrice Chotard <patrice.chotard at st.com>
> > Cc: Patrick Delaunay <patrick.delaunay at st.com>
> > Cc: Ramon Fried <rfried.dev at gmail.com>
> > Cc: Stephen Warren <swarren at nvidia.com>
> > ---
> For the series,
> Tested-by: Patrick Delaunay <patrick.delaunay at st.com> (on STM32MP15C-DK2,
> manual test: dhcp and run bootcmd_pxe)

To complete my test and to check the cache management in the driver,

I test the sequence (CONFIG_SYS_NONCACHED_MEMORY is activated):

1) ping with dcache ON: Always OK

STM32MP> dhcp
STM32MP> ping

2) ping with dcache OFF : Always OK

STM32MP> dcache off 
STM32MP> ping 

3) ping with dcache ON : Failed 

STM32MP> dcache on 
STM32MP> ping

Failed with "eqos_send: TX timeout"
and after "eqos_recv: RX packet not available"

4) ping with dcache OFF : Always OK

STM32MP> dcache on 
STM32MP> ping

I don't sure this sequence is really valid 
or if this issue show a problem in cache management.

As I don't see any obvious issue in eqos_send,
do you idea on reason of this issue ?

> Regards
> Patrick

More information about the U-Boot mailing list