[PATCH v2 2/3] arm: dts: arria10: Update dtsi/dts from Linux
Simon Goldschmidt
simon.k.r.goldschmidt at gmail.com
Wed Apr 8 07:56:32 CEST 2020
On Tue, Apr 7, 2020 at 9:43 AM Ley Foon Tan <ley.foon.tan at intel.com> wrote:
>
> Update these 3 files from Linux:.
> - socfpga_arria10.dtsi (Commit ID c1459a9d7e92)
> - socfpga_arria10_socdk.dtsi (Commit ID d9b9f805ee2b)
> - socfpga_arria10_socdk_sdmmc.dts (Commit ID 17808d445b6f)
>
> Change in socfpga_arria10.dtsi:
> - Add clkmgr label, so that can reference to it in u-boot.dtsi.
>
> Change in socfpga_arria10-u-boot.dtsi:
> - Add compatible and altr,sysmgr-syscon for uboot.
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
>
> ---
> v2: Update commit ID in description.
> ---
> arch/arm/dts/socfpga_arria10-u-boot.dtsi | 15 ++++
> arch/arm/dts/socfpga_arria10.dtsi | 90 ++++++++++++++------
> arch/arm/dts/socfpga_arria10_socdk.dtsi | 43 +++++++---
> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 16 +---
> 4 files changed, 108 insertions(+), 56 deletions(-)
>
> diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> index c637b100738a..0db358cf1f2b 100644
> --- a/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> @@ -38,6 +38,21 @@
> u-boot,dm-pre-reloc;
> };
>
> +&gmac0 {
> + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
> + altr,sysmgr-syscon = <&sysmgr 0x44 0>;
> +};
> +
> +&gmac1 {
> + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
> + altr,sysmgr-syscon = <&sysmgr 0x48 0>;
> +};
> +
> +&gmac2 {
> + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
> + altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
> +};
> +
> &i2c0 {
> reset-names = "i2c";
> };
> diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
> index c8cd5a84b8a8..a598c7554266 100644
> --- a/arch/arm/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/dts/socfpga_arria10.dtsi
> @@ -1,17 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0
> /*
> * Copyright Altera Corporation (C) 2014. All rights reserved.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms and conditions of the GNU General Public License,
> - * version 2, as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope it will be useful, but WITHOUT
> - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> - * more details.
> - *
> - * You should have received a copy of the GNU General Public License along with
> - * this program. If not, see <http://www.gnu.org/licenses/>.
> */
>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -79,6 +68,8 @@
> #dma-requests = <32>;
> clocks = <&l4_main_clk>;
> clock-names = "apb_pclk";
> + resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
> + reset-names = "dma", "dma-ocp";
> };
> };
>
> @@ -377,13 +368,28 @@
> clk-gate = <0xC8 11>;
> };
>
> - nand_clk: nand_clk {
> + nand_x_clk: nand_x_clk {
> #clock-cells = <0>;
> compatible = "altr,socfpga-a10-gate-clk";
> clocks = <&l4_mp_clk>;
> clk-gate = <0xC8 10>;
> };
>
> + nand_ecc_clk: nand_ecc_clk {
> + #clock-cells = <0>;
> + compatible = "altr,socfpga-a10-gate-clk";
> + clocks = <&nand_x_clk>;
> + clk-gate = <0xC8 10>;
> + };
> +
> + nand_clk: nand_clk {
> + #clock-cells = <0>;
> + compatible = "altr,socfpga-a10-gate-clk";
> + clocks = <&nand_x_clk>;
> + fixed-divider = <4>;
> + clk-gate = <0xC8 10>;
> + };
> +
> spi_m_clk: spi_m_clk {
> #clock-cells = <0>;
> compatible = "altr,socfpga-a10-gate-clk";
> @@ -414,7 +420,7 @@
> };
>
> gmac0: ethernet at ff800000 {
> - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
> + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
> altr,sysmgr-syscon = <&sysmgr 0x44 0>;
> reg = <0xff800000 0x2000>;
> interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
> @@ -434,8 +440,8 @@
> };
>
> gmac1: ethernet at ff802000 {
> - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
> - altr,sysmgr-syscon = <&sysmgr 0x48 0>;
> + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
> + altr,sysmgr-syscon = <&sysmgr 0x48 8>;
> reg = <0xff802000 0x2000>;
> interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "macirq";
> @@ -454,8 +460,8 @@
> };
>
> gmac2: ethernet at ff804000 {
> - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
> - altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
> + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
> + altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
> reg = <0xff804000 0x2000>;
> interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "macirq";
> @@ -478,6 +484,7 @@
> #size-cells = <0>;
> compatible = "snps,dw-apb-gpio";
> reg = <0xffc02900 0x100>;
> + resets = <&rst GPIO0_RESET>;
> status = "disabled";
>
> porta: gpio-controller at 0 {
> @@ -497,6 +504,7 @@
> #size-cells = <0>;
> compatible = "snps,dw-apb-gpio";
> reg = <0xffc02a00 0x100>;
> + resets = <&rst GPIO1_RESET>;
> status = "disabled";
>
> portb: gpio-controller at 0 {
> @@ -516,6 +524,7 @@
> #size-cells = <0>;
> compatible = "snps,dw-apb-gpio";
> reg = <0xffc02b00 0x100>;
> + resets = <&rst GPIO2_RESET>;
> status = "disabled";
>
> portc: gpio-controller at 0 {
> @@ -594,22 +603,35 @@
> status = "disabled";
> };
>
> + spi0: spi at ffda4000 {
> + compatible = "snps,dw-apb-ssi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0xffda4000 0x100>;
> + interrupts = <0 101 4>;
> + num-cs = <4>;
> + /*32bit_access;*/
> + clocks = <&spi_m_clk>;
> + resets = <&rst SPIM0_RESET>;
> + status = "disabled";
> + };
> +
> spi1: spi at ffda5000 {
> compatible = "snps,dw-apb-ssi";
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0xffda5000 0x100>;
> interrupts = <0 102 4>;
> - num-chipselect = <4>;
> - bus-num = <0>;
> + num-cs = <4>;
> /*32bit_access;*/
> tx-dma-channel = <&pdma 16>;
> rx-dma-channel = <&pdma 17>;
> clocks = <&spi_m_clk>;
> + resets = <&rst SPIM1_RESET>;
> status = "disabled";
> };
>
> - sdr: sdr at ffc25000 {
> + sdr: sdr at ffcfb100 {
> compatible = "altr,sdr-ctl", "syscon";
> reg = <0xffcfb100 0x80>;
> };
> @@ -640,14 +662,14 @@
>
> nand: nand at ffb90000 {
> #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
> - reg = <0xffb90000 0x20>,
> - <0xffb80000 0x1000>;
> + #size-cells = <0>;
> + compatible = "altr,socfpga-denali-nand";
> + reg = <0xffb90000 0x72000>,
> + <0xffb80000 0x10000>;
> reg-names = "nand_data", "denali_reg";
> interrupts = <0 99 4>;
> - dma-mask = <0xffffffff>;
> - clocks = <&nand_clk>;
> + clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
> + clock-names = "nand", "nand_x", "ecc";
> resets = <&rst NAND_RESET>;
> status = "disabled";
> };
> @@ -733,6 +755,8 @@
> cdns,fifo-width = <4>;
> cdns,trigger-address = <0x00000000>;
> clocks = <&qspi_clk>;
> + resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
> + reset-names = "qspi", "qspi-ocp";
> status = "disabled";
> };
>
> @@ -758,7 +782,7 @@
> timer at ffffc600 {
> compatible = "arm,cortex-a9-twd-timer";
> reg = <0xffffc600 0x100>;
> - interrupts = <1 13 0xf04>;
> + interrupts = <1 13 0xf01>;
> clocks = <&mpu_periph_clk>;
> };
>
> @@ -768,6 +792,8 @@
> reg = <0xffc02700 0x100>;
> clocks = <&l4_sp_clk>;
> clock-names = "timer";
> + resets = <&rst SPTIMER0_RESET>;
> + reset-names = "timer";
> };
>
> timer1: timer1 at ffc02800 {
> @@ -776,6 +802,8 @@
> reg = <0xffc02800 0x100>;
> clocks = <&l4_sp_clk>;
> clock-names = "timer";
> + resets = <&rst SPTIMER1_RESET>;
> + reset-names = "timer";
> };
>
> timer2: timer2 at ffd00000 {
> @@ -784,6 +812,8 @@
> reg = <0xffd00000 0x100>;
> clocks = <&l4_sys_free_clk>;
> clock-names = "timer";
> + resets = <&rst L4SYSTIMER0_RESET>;
> + reset-names = "timer";
> };
>
> timer3: timer3 at ffd00100 {
> @@ -792,6 +822,8 @@
> reg = <0xffd01000 0x100>;
> clocks = <&l4_sys_free_clk>;
> clock-names = "timer";
> + resets = <&rst L4SYSTIMER1_RESET>;
> + reset-names = "timer";
> };
>
> uart0: serial0 at ffc02000 {
> @@ -853,6 +885,7 @@
> reg = <0xffd00200 0x100>;
> interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&l4_sys_free_clk>;
> + resets = <&rst L4WD0_RESET>;
> status = "disabled";
> };
>
> @@ -861,6 +894,7 @@
> reg = <0xffd00300 0x100>;
> interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&l4_sys_free_clk>;
> + resets = <&rst L4WD1_RESET>;
> status = "disabled";
> };
> };
> diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> index e704243c14c1..0efbeccc5cd2 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
> +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> @@ -1,20 +1,7 @@
> +// SPDX-License-Identifier: GPL-2.0+
> /*
> * Copyright (C) 2015 Altera Corporation <www.altera.com>
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program. If not, see <http://www.gnu.org/licenses/>.
> */
> -
> #include "socfpga_arria10.dtsi"
>
> / {
> @@ -61,6 +48,22 @@
> };
> };
>
> + ref_033v: 033-v-ref {
> + compatible = "regulator-fixed";
> + regulator-name = "0.33V";
> + regulator-min-microvolt = <330000>;
> + regulator-max-microvolt = <330000>;
> + };
> +
> + soc {
> + clkmgr at ffd04000 {
> + clocks {
> + osc1 {
> + clock-frequency = <25000000>;
> + };
> + };
> + };
> + };
> };
>
> &gmac0 {
> @@ -132,6 +135,18 @@
> i2c-sda-falling-time-ns = <6000>;
> i2c-scl-falling-time-ns = <6000>;
>
> + adc at 14 {
> + compatible = "lltc,ltc2497";
> + reg = <0x14>;
> + vref-supply = <&ref_033v>;
> + };
> +
> + adc at 16 {
> + compatible = "lltc,ltc2497";
> + reg = <0x16>;
> + vref-supply = <&ref_033v>;
> + };
> +
> eeprom at 51 {
> compatible = "atmel,24c32";
> reg = <0x51>;
> diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> index 040a164ba148..64dc0799f3d7 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> @@ -1,18 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> /*
> * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program. If not, see <http://www.gnu.org/licenses/>.
> */
>
> /dts-v1/;
> @@ -20,8 +8,8 @@
>
> &mmc {
> status = "okay";
> - num-slots = <1>;
> cap-sd-highspeed;
> + cap-mmc-highspeed;
> broken-cd;
> bus-width = <4>;
> };
> --
> 2.19.0
>
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