[PATCH v8 13/21] riscv: Clear pending interrupts before enabling IPIs
Sean Anderson
seanga2 at gmail.com
Fri Apr 10 14:28:06 CEST 2020
On some platforms (k210), the previous stage bootloader may have not
cleared pending IPIs before transferring control to U-Boot. This can cause
race conditions, as multiple harts all attempt to initialize the IPI
controller at once. This patch clears IPIs before enabling them, ensuring
that only one hart modifies shared memory at once.
Signed-off-by: Sean Anderson <seanga2 at gmail.com>
Reviewed-by: Rick Chen <rick at andestech.com>
---
Changes in v7:
- Split of into its own patch
arch/riscv/cpu/start.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 6b3ff99c38..e8740c8568 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -67,6 +67,8 @@ _start:
#else
li t0, SIE_SSIE
#endif
+ /* Clear any pending IPIs */
+ csrc MODE_PREFIX(ip), t0
csrs MODE_PREFIX(ie), t0
#endif
--
2.25.1
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