[PATCH 2/7] riscv: Merge unnecessary SMP ifdefs in start.S

[Atish Patra]

On Wed, Apr 8, 2020 at 6:41 AM Bin Meng <bmeng.cn at gmail.com> wrote:
>
> Two consecutive SMP ifdefs blocks can be combined into one.
>
> Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
> ---
>
>  arch/riscv/cpu/start.S | 4 ----
>  1 file changed, 4 deletions(-)
>
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index 6b3ff99..ecf0482 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -58,9 +58,7 @@ _start:
>         /* tp: hart id */
>         li      t0, CONFIG_NR_CPUS
>         bge     tp, t0, hart_out_of_bounds_loop
> -#endif
>
> -#ifdef CONFIG_SMP
>         /* set xSIE bit to receive IPIs */
>  #if CONFIG_IS_ENABLED(RISCV_MMODE)
>         li      t0, MIE_MSIE
> @@ -377,9 +375,7 @@ hart_out_of_bounds_loop:
>         /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */
>         wfi
>         j       hart_out_of_bounds_loop
> -#endif
>
> -#ifdef CONFIG_SMP
>  /* SMP relocation entry */
>  secondary_hart_relocate:
>         /* a1: new sp */
> --
> 2.7.4
>

Reviewed-by: Atish Patra <atish.patra at wdc.com>

-- 
Regards,
Atish