[PATCH v2 5/5] azure/gitlab/travis: Add RISC-V SPL testing

[Tom Rini]

On Sat, Mar 28, 2020 at 07:25:29AM -0700, Bin Meng wrote:

> This adds QEMU RISC-V 32/64 SPL testing. Unlike QEMU RISC-V 32/64,
> we test SPL running in M-mode and U-Boot proper running in S-mode,
> with a 4-core SMP configuration.
> 
> Signed-off-by: Bin Meng <bmeng.cn at gmail.com>

Applied to u-boot/next, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 659 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200410/e4fd82c9/attachment.sig>