[PATCH 04/27] dm: powerpc: P5040DS: add i2c DM support

[Priyanka Jain (OSS)]

>-----Original Message-----
>From: U-Boot <u-boot-bounces at lists.denx.de> On Behalf Of Biwen Li
>Sent: Sunday, April 12, 2020 2:24 PM
>To: Jagdish Gediya <jagdish.gediya at nxp.com>; Priyanka Jain
><priyanka.jain at nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
>aford173 at gmail.com; Alison Wang <alison.wang at nxp.com>;
>jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1 at nxp.com>;
>Rajesh Bhagat <rajesh.bhagat at nxp.com>; Ruchika Gupta
><ruchika.gupta at nxp.com>; olteanv at gmail.com
>Cc: Xiaobo Xie <xiaobo.xie at nxp.com>; Jiafei Pan <jiafei.pan at nxp.com>; u-
>boot at lists.denx.de; Z.q. Hou <zhiqiang.hou at nxp.com>; Biwen Li
><biwen.li at nxp.com>
>Subject: [PATCH 04/27] dm: powerpc: P5040DS: add i2c DM support
>
>From: Biwen Li <biwen.li at nxp.com>
>
>This supports i2c DM for board P5040DS
>
>Signed-off-by: Biwen Li <biwen.li at nxp.com>
>---
> arch/powerpc/dts/p5040.dtsi  | 5 ++++-
> include/configs/corenet_ds.h | 8 +++++++-
> 2 files changed, 11 insertions(+), 2 deletions(-)
>
>diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi
>index 67a62a7725..45988574a2 100644
>--- a/arch/powerpc/dts/p5040.dtsi
>+++ b/arch/powerpc/dts/p5040.dtsi
>@@ -3,7 +3,7 @@
>  * P5040 Silicon/SoC Device Tree Source (pre include)
>  *
>  * Copyright 2012 - 2015 Freescale Semiconductor Inc.
>- * Copyright 2019 NXP
>+ * Copyright 2019-2020 NXP
>  */
>
> /dts-v1/;
>@@ -85,6 +85,9 @@
> 			reg = <0x114000 0x1000>;
> 			clock-frequency = <0>;
> 		};
>+
>+		/include/ "qoriq-i2c-0.dtsi"
>+		/include/ "qoriq-i2c-1.dtsi"
> 	};
>
> 	pcie at ffe200000 {
>diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index
>bafedcb0d2..d8402e493d 100644
>--- a/include/configs/corenet_ds.h
>+++ b/include/configs/corenet_ds.h
Biwen,

Please confirm that P5040DS is the only board using corenet_ds.h file

Regards
Priyanka
>@@ -1,6 +1,7 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /*
>  * Copyright 2009-2012 Freescale Semiconductor, Inc.
>+ * Copyright 2020 NXP
>  */
>
> /*
>@@ -276,14 +277,19 @@
> #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
>
> /* I2C */
>+#ifndef CONFIG_DM_I2C
> #define CONFIG_SYS_I2C
>-#define CONFIG_SYS_I2C_FSL
> #define CONFIG_SYS_FSL_I2C_SPEED	400000
> #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
> #define CONFIG_SYS_FSL_I2C2_SPEED	400000
> #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
>+#else
>+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
>+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
>+#endif
>+#define CONFIG_SYS_I2C_FSL
>
> /*
>  * RapidIO
>--
>2.17.1