[PATCH v3 1/3] spi: sifive: Fix QPP transfer

[Bin Meng]

Hi Jagan,

On Mon, Apr 20, 2020 at 10:09 PM Jagan Teki <jagan at amarulasolutions.com> wrote:
>
> On Mon, Apr 20, 2020 at 7:31 PM Bin Meng <bmeng.cn at gmail.com> wrote:
> >
> > Hi Jagan,
> >
> > On Mon, Apr 20, 2020 at 8:52 PM Jagan Teki <jagan at amarulasolutions.com> wrote:
> > >
> > > For historical reasons the existing logic of filling tx fifo
> >
> > What historical reasons?
>
> No real idea, seems like exciting logic is developed to make mmc_spi workable.

Could you put such "guessed reason" other than "historical" in the
commit message, to help better understanding?

>
> >
> > > with data, rx fifo with NULL for tx transfer and filling rx
> > > fifo with data, tx fifo with NULL for rx transfer is not
> > > clear enough to support the Quad Page Program.
> > >
> > > SiFive SPI controllers have specific sets of watermark
> > > registers and SPI I/O directions bits in order to program
> > > SPI controllers clear enough to support all sets of operating
> > > modes.
> > >
> > > Here is the exact programing sequence that would follow on this
> > > patch and tested via SPI-NOR and MMC_SPI.
> > >
> > > - set the frame format proto, endian
> > > - set the frame format dir, set it for tx and clear it for rx
> > > - TX transfer:
> > >   fill tx fifo with data.
> > >   wait for TX watermark bit to clear.
> > > - TX transfer:
> >
> > RX transfer ?
>
> Thanks, my bad.
>
> >
> > >   fill tx fifo with 0xff.
> >
> > rx fifo ?
>
> No it is rx fifo in order to read the rx fifo we need to pass 0xff to

I assume here it is tx fifo

> tx fifo, typical SPI protocol.

Regards
Bin