[PATCHv2 6/9] arm64: layerscape: Move GIC RD tables initialization to CPU setup function
Wasim Khan
wasim.khan at nxp.com
Tue Apr 21 09:39:51 CEST 2020
> -----Original Message-----
> From: U-Boot <u-boot-bounces at lists.denx.de> On Behalf Of Zhiqiang Hou
> Sent: Tuesday, March 24, 2020 1:42 PM
> To: u-boot at lists.denx.de; Priyanka Jain <priyanka.jain at nxp.com>; Biwen Li
> <biwen.li at nxp.com>
> Cc: Z.q. Hou <zhiqiang.hou at nxp.com>
> Subject: [PATCHv2 6/9] arm64: layerscape: Move GIC RD tables initialization to
> CPU setup function
>
> From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
>
> Move GIC redistributor tables initialization to CPU setup function.
>
> This patch introduces a GIC redistributor tables init function, and moves the
> function of reserving memory for GIC redistributor tables to soc.c and adds a
> argument for the memory size to reserve, BTW rename the function so that it is
> more readable.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
Reviewed-by: Wasim Khan <wasim.khan at nxp.com>
> ---
> V2:
> - New patch.
>
> arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 4 ++
> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 44 +++++++++++++++++++
> .../arm/include/asm/arch-fsl-layerscape/soc.h | 4 ++
> board/freescale/lx2160a/lx2160a.c | 28 ------------
> 4 files changed, 52 insertions(+), 28 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-
> layerscape/fdt.c
> index 87c3e05f45..36e0a2380e 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> @@ -462,6 +462,10 @@ void ft_cpu_setup(void *blob, bd_t *bd)
> do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
> CONFIG_SYS_CLK_FREQ, 1);
>
> +#ifdef CONFIG_GIC_V3_ITS
> + ls_gic_rd_tables_init(blob);
> +#endif
> +
> #if defined(CONFIG_PCIE_LAYERSCAPE) ||
> defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
> ft_pci_setup(blob, bd);
> #endif
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index d0e10cb007..28bb1d7401 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -6,10 +6,12 @@
>
> #include <common.h>
> #include <clock_legacy.h>
> +#include <cpu_func.h>
> #include <env.h>
> #include <fsl_immap.h>
> #include <fsl_ifc.h>
> #include <init.h>
> +#include <linux/sizes.h>
> #include <asm/arch/fsl_serdes.h>
> #include <asm/arch/soc.h>
> #include <asm/io.h>
> @@ -17,6 +19,7 @@
> #include <asm/arch-fsl-layerscape/config.h>
> #include <asm/arch-fsl-layerscape/ns_access.h>
> #include <asm/arch-fsl-layerscape/fsl_icid.h>
> +#include <asm/gic-v3.h>
> #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
> #include <fsl_csu.h>
> #endif
> @@ -30,9 +33,50 @@
> #include <fsl_immap.h>
> #ifdef CONFIG_TFABOOT
> #include <env_internal.h>
> +#endif
> +#if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
> DECLARE_GLOBAL_DATA_PTR;
> #endif
>
> +#ifdef CONFIG_GIC_V3_ITS
> +#define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
> +#define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
> +#define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ
> + \
> + PROPTABLE_MAX_SZ, SZ_1M)
> +static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t
> +size) {
> + u32 phandle;
> + int err;
> + struct fdt_memory gic_rd_tables;
> +
> + gic_rd_tables.start = base;
> + gic_rd_tables.end = base + size - 1;
> + err = fdtdec_add_reserved_memory(blob, "gic-rd-tables",
> &gic_rd_tables,
> + &phandle);
> + if (err < 0)
> + debug("%s: failed to add reserved memory: %d\n", __func__,
> err);
> +
> + return err;
> +}
> +
> +int ls_gic_rd_tables_init(void *blob)
> +{
> + u64 gic_lpi_base;
> + int ret;
> +
> + gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
> + ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base,
> GIC_LPI_SIZE);
> + if (ret)
> + return ret;
> +
> + ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
> + if (ret)
> + debug("%s: failed to init gic-lpi-tables\n", __func__);
> +
> + return ret;
> +}
> +#endif
> +
> bool soc_has_dp_ddr(void)
> {
> struct ccsr_gur __iomem *gur = (void
> *)(CONFIG_SYS_FSL_GUTS_ADDR); diff --git a/arch/arm/include/asm/arch-fsl-
> layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> index c62d414aac..020548ac6c 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> @@ -158,6 +158,10 @@ void erratum_a010315(void);
>
> bool soc_has_dp_ddr(void);
> bool soc_has_aiop(void);
> +
> +#ifdef CONFIG_GIC_V3_ITS
> +int ls_gic_rd_tables_init(void *blob);
> +#endif
> #endif
>
> #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git
> a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
> index c8e962ce3d..cd6a9a34ac 100644
> --- a/board/freescale/lx2160a/lx2160a.c
> +++ b/board/freescale/lx2160a/lx2160a.c
> @@ -5,7 +5,6 @@
>
> #include <common.h>
> #include <clock_legacy.h>
> -#include <cpu_func.h>
> #include <dm.h>
> #include <dm/platform_data/serial_pl01x.h> #include <i2c.h> @@ -17,7 +16,6
> @@ #include <asm/io.h> #include <fdt_support.h> #include <linux/libfdt.h> -
> #include <linux/sizes.h> #include <fsl-mc/fsl_mc.h> #include <env_internal.h>
> #include <efi_loader.h> @@ -31,13 +29,11 @@ #include "../common/vid.h"
> #include <fsl_immap.h>
> #include <asm/arch-fsl-layerscape/fsl_icid.h>
> -#include <asm/gic-v3.h>
>
> #ifdef CONFIG_EMC2305
> #include "../common/emc2305.h"
> #endif
>
> -#define GIC_LPI_SIZE 0x200000
> #ifdef CONFIG_TARGET_LX2160AQDS
> #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
> #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
> @@ -631,21 +627,6 @@ void board_quiesce_devices(void) } #endif
>
> -#ifdef CONFIG_GIC_V3_ITS
> -void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base) -{
> - u32 phandle;
> - int err;
> - struct fdt_memory gic_lpi;
> -
> - gic_lpi.start = gic_lpi_base;
> - gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1;
> - err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle);
> - if (err < 0)
> - debug("failed to add reserved memory: %d\n", err);
> -}
> -#endif
> -
> #ifdef CONFIG_OF_BOARD_SETUP
> int ft_board_setup(void *blob, bd_t *bd) { @@ -657,8 +638,6 @@ int
> ft_board_setup(void *blob, bd_t *bd)
> u64 mc_memory_base = 0;
> u64 mc_memory_size = 0;
> u16 total_memory_banks;
> - u64 gic_lpi_base;
> - int ret;
>
> ft_cpu_setup(blob, bd);
>
> @@ -678,13 +657,6 @@ int ft_board_setup(void *blob, bd_t *bd)
> size[i] = gd->bd->bi_dram[i].size;
> }
>
> -#ifdef CONFIG_GIC_V3_ITS
> - gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
> - ret = fdt_fixup_gic_lpi_memory(blob, gic_lpi_base);
> - if (!ret && gic_lpi_tables_init(gic_lpi_base, cpu_numcores()))
> - debug("%s: failed to init gic-lpi-tables\n", __func__);
> -#endif
> -
> #ifdef CONFIG_RESV_RAM
> /* reduce size if reserved memory is within this bank */
> if (gd->arch.resv_ram >= base[0] &&
> --
> 2.17.1
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