[PATCH v1 1/3] drivers: pinctrl-single: handle different register width

[Rayagonda Kokatanur]

On Wed, Apr 29, 2020 at 11:34 PM Simon Glass <sjg at chromium.org> wrote:
>
> Hi Rayagonda,
>
> +Stephen Warren
>
> On Wed, 29 Apr 2020 at 10:35, Rayagonda Kokatanur
> <rayagonda.kokatanur at broadcom.com> wrote:
> >
> > Add support to use different register read/write api's
> > based on register width.
> >
> > Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur at broadcom.com>
> > ---
> >  drivers/pinctrl/pinctrl-single.c | 98 ++++++++++++++++++++++++--------
> >  1 file changed, 74 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
> > index 738f5bd636..aed113b083 100644
> > --- a/drivers/pinctrl/pinctrl-single.c
> > +++ b/drivers/pinctrl/pinctrl-single.c
> > @@ -10,12 +10,24 @@
> >  #include <linux/libfdt.h>
> >  #include <asm/io.h>
> >
> > +/**
> > + * struct single_pdata - pinctrl device instance
> > + * @base       first configuration register
> > + * @offset     index of last configuration register
> > + * @mask       configuration-value mask bits
> > + * @width      configuration register bit width
> > + * @bits_per_mux
> > + * @read       register read function to use
> > + * @write      register write function to use
> > + */
> >  struct single_pdata {
> >         fdt_addr_t base;        /* first configuration register */
> >         int offset;             /* index of last configuration register */
> >         u32 mask;               /* configuration-value mask bits */
> >         int width;              /* configuration register bit width */
> >         bool bits_per_mux;
> > +       u32 (*read)(phys_addr_t reg);
> > +       void (*write)(u32 val, phys_addr_t reg);
>
> Can't we just have a read & write function with a switch statement?
> Why do we need function pointers?

I referred to the linux pinctrl-single.c and kept code similar to linux.
Please let me know.

>
> Regards,
> Simon