[PATCH] ARM: dts: stm32: Switch to MCO2 for PHY 50 MHz clock

[Patrice CHOTARD]

Hi Marek

On 12/1/20 11:34 AM, Marek Vasut wrote:
> The LAN8710i PHY currently uses 50 MHz clock direct from PLL4P.
> To permit PLL4P to run at faster frequency, use MCO2 as a divider.
> The PLL4P runs at 100 MHz, supplies MCO2 which divides it by 2 to
> 50MHz, and supplies the PHY with 50 MHz via pin PG2. The feedback
> clock are fed back in via pin PA1.
>
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Patrice Chotard <patrice.chotard at st.com>
> Cc: Patrick Delaunay <patrick.delaunay at st.com>
> ---
> NOTE: This is for next
> ---
>  arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 25 +++++++++++++++++-----
>  arch/arm/dts/stm32mp15xx-dhcom.dtsi        |  3 +--
>  2 files changed, 21 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> index 92345b7ba3..6868769c6e 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> @@ -72,8 +72,8 @@
>  
>  &pinctrl {
>  	/* These should bound to FMC2 bus driver, but we do not have one */
> -	pinctrl-0 = <&fmc_pins_b>;
> -	pinctrl-1 = <&fmc_sleep_pins_b>;
> +	pinctrl-0 = <&fmc_pins_b &mco2_pins_a>;
> +	pinctrl-1 = <&fmc_sleep_pins_b &mco2_sleep_pins_a>;
>  	pinctrl-names = "default", "sleep";
>  
>  	fmc_pins_b: fmc-0 {
> @@ -130,6 +130,21 @@
>  				 <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
>  		};
>  	};
> +
> +	mco2_pins_a: mco2-0 {
> +		pins {
> +			pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
> +			bias-disable;
> +			drive-push-pull;
> +			slew-rate = <2>;
> +		};
> +	};
> +
> +	mco2_sleep_pins_a: mco2-sleep-0 {
> +		pins {
> +			pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
> +		};
> +	};
>  };
>  
>  &pmic {
> @@ -181,7 +196,7 @@
>  		CLK_PLL4_HSE
>  		CLK_RTC_LSE
>  		CLK_MCO1_DISABLED
> -		CLK_MCO2_DISABLED
> +		CLK_MCO2_PLL4P
>  	>;
>  
>  	st,clkdiv = <
> @@ -195,7 +210,7 @@
>  		2 /*APB5*/
>  		23 /*RTC*/
>  		0 /*MCO1*/
> -		0 /*MCO2*/
> +		1 /*MCO2*/
>  	>;
>  
>  	st,pkcs = <
> @@ -258,7 +273,7 @@
>  	pll4: st,pll at 3 {
>  		compatible = "st,stm32mp1-pll";
>  		reg = <3>;
> -		cfg = < 1 49 11 11 11 PQR(1,1,1) >;
> +		cfg = < 1 49 5 11 11 PQR(1,1,1) >;
>  		u-boot,dm-pre-reloc;
>  	};
>  };
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
> index dafcce4323..a1d1b8dec7 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi
> +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
> @@ -58,7 +58,6 @@
>  	phy-mode = "rmii";
>  	max-speed = <100>;
>  	phy-handle = <&phy0>;
> -	st,eth_ref_clk_sel;
>  	phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
>  
>  	mdio0 {
> @@ -267,7 +266,7 @@
>  			pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
>  				 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
>  				 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
> -				 <STM32_PINMUX('A', 1, AF0)>,   /* ETH1_RMII_REF_CLK */
> +				 <STM32_PINMUX('A', 1, AF11)>,  /* ETH1_RMII_REF_CLK */
>  				 <STM32_PINMUX('A', 2, AF11)>,  /* ETH1_MDIO */
>  				 <STM32_PINMUX('C', 1, AF11)>;  /* ETH1_MDC */
>  			bias-disable;

Reviewed-by: Patrice Chotard <patrice.chotard at st.com>

Thanks

Patrice