[PATCH 01/34] ARM: dts: sama7g5: add initial DT for sama7g5 SoC

[Eugen Hristev]

Add initial basic devicetree for sama7g5 SoC

Signed-off-by: Eugen Hristev <eugen.hristev at microchip.com>
---
 arch/arm/dts/sama7g5.dtsi | 65 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 arch/arm/dts/sama7g5.dtsi

diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi
new file mode 100644
index 0000000000..24b6f90957
--- /dev/null
+++ b/arch/arm/dts/sama7g5.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sama7g5.dtsi - Device Tree Include file for SAMA7G5 SoC.
+ *
+ * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Eugen Hristev <eugen.hristev at microchip.com>
+ * Author: Claudiu Beznea <claudiu.beznea at microchip.com>
+ *
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+	model = "Microchip SAMA7G5 family SoC";
+	compatible = "microchip,sama7g5";
+
+	clocks {
+		slow_xtal: slow_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+
+		main_xtal: main_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+
+		mck: mck {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+		};
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		apb {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			sdmmc1: sdio-host at e1208000 {
+				compatible = "microchip,sama7g5-sdhci";
+				reg = <0xe1208000 0x300>;
+				clocks = <&mck>, <&mck>, <&mck>;
+				clock-names = "hclock", "multclk", "baseclk";
+				status = "disabled";
+			};
+
+			uart0: serial at e1824200 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xe1824200 0x200>;
+				clocks = <&mck>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+		};
+	};
+};
-- 
2.25.1