[PATCH] arm: dts: k3-j721e: ddr: Update to 0.5.0 version of DDR config tool
praneeth at ti.com
praneeth at ti.com
Fri Dec 4 00:43:47 CET 2020
From: Praneeth Bajjuri <praneeth at ti.com>
Update the ddr settings to use the DDR reg config tool rev 0.5.0.
This enables 4266MTs DDR configuration.
Signed-off-by: Praneeth Bajjuri <praneeth at ti.com>
Signed-off-by: Kevin Scholz <k-scholz at ti.com>
---
...33.dtsi => k3-j721e-ddr-evm-lp4-4266.dtsi} | 436 +++++++++---------
.../arm/dts/k3-j721e-r5-common-proc-board.dts | 2 +-
2 files changed, 219 insertions(+), 219 deletions(-)
rename arch/arm/dts/{k3-j721e-ddr-evm-lp4-3733.dtsi => k3-j721e-ddr-evm-lp4-4266.dtsi} (90%)
diff --git a/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi
similarity index 90%
rename from arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi
rename to arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi
index 5ac32a0ffa..ca05e06e93 100644
--- a/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi
+++ b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi
@@ -1,13 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- * This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool, Revision: 0.2.0
- * This file was generated on 10/09/2019
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.5.0
+ * This file was generated on 09/25/2020
*/
#define DDRSS_PLL_FHS_CNT 10
-#define DDRSS_PLL_FREQUENCY_1 933000000
-#define DDRSS_PLL_FREQUENCY_2 933000000
+#define DDRSS_PLL_FREQUENCY_1 1066500000
+#define DDRSS_PLL_FREQUENCY_2 1066500000
#define DDRSS_CTL_00_DATA 0x00000B00
#define DDRSS_CTL_01_DATA 0x00000000
@@ -20,14 +20,14 @@
#define DDRSS_CTL_08_DATA 0x000186A0
#define DDRSS_CTL_09_DATA 0x00000005
#define DDRSS_CTL_10_DATA 0x00000064
-#define DDRSS_CTL_11_DATA 0x0005B18F
-#define DDRSS_CTL_12_DATA 0x0038EF90
+#define DDRSS_CTL_11_DATA 0x000681C8
+#define DDRSS_CTL_12_DATA 0x004111C9
#define DDRSS_CTL_13_DATA 0x00000005
-#define DDRSS_CTL_14_DATA 0x00000E94
-#define DDRSS_CTL_15_DATA 0x0005B18F
-#define DDRSS_CTL_16_DATA 0x0038EF90
+#define DDRSS_CTL_14_DATA 0x000010A9
+#define DDRSS_CTL_15_DATA 0x000681C8
+#define DDRSS_CTL_16_DATA 0x004111C9
#define DDRSS_CTL_17_DATA 0x00000005
-#define DDRSS_CTL_18_DATA 0x00000E94
+#define DDRSS_CTL_18_DATA 0x000010A9
#define DDRSS_CTL_19_DATA 0x01010000
#define DDRSS_CTL_20_DATA 0x02011001
#define DDRSS_CTL_21_DATA 0x02010000
@@ -37,66 +37,66 @@
#define DDRSS_CTL_25_DATA 0x00000000
#define DDRSS_CTL_26_DATA 0x00000000
#define DDRSS_CTL_27_DATA 0x02020200
-#define DDRSS_CTL_28_DATA 0x00004B4B
+#define DDRSS_CTL_28_DATA 0x00005656
#define DDRSS_CTL_29_DATA 0x00100000
#define DDRSS_CTL_30_DATA 0x00000000
#define DDRSS_CTL_31_DATA 0x00000000
#define DDRSS_CTL_32_DATA 0x00000000
#define DDRSS_CTL_33_DATA 0x00000000
#define DDRSS_CTL_34_DATA 0x040C0000
-#define DDRSS_CTL_35_DATA 0x10401040
+#define DDRSS_CTL_35_DATA 0x12481248
#define DDRSS_CTL_36_DATA 0x00050804
#define DDRSS_CTL_37_DATA 0x09040008
-#define DDRSS_CTL_38_DATA 0x12000204
-#define DDRSS_CTL_39_DATA 0x1854007A
-#define DDRSS_CTL_40_DATA 0x12003A26
-#define DDRSS_CTL_41_DATA 0x1854007A
-#define DDRSS_CTL_42_DATA 0x20003A26
+#define DDRSS_CTL_38_DATA 0x15000204
+#define DDRSS_CTL_39_DATA 0x1B60008B
+#define DDRSS_CTL_40_DATA 0x1500422B
+#define DDRSS_CTL_41_DATA 0x1B60008B
+#define DDRSS_CTL_42_DATA 0x2000422B
#define DDRSS_CTL_43_DATA 0x000A0A09
#define DDRSS_CTL_44_DATA 0x040006DB
-#define DDRSS_CTL_45_DATA 0x1B130F04
-#define DDRSS_CTL_46_DATA 0x0E00FFCD
-#define DDRSS_CTL_47_DATA 0x1B130F0E
-#define DDRSS_CTL_48_DATA 0x0E00FFCD
-#define DDRSS_CTL_49_DATA 0x0203040E
-#define DDRSS_CTL_50_DATA 0x26040500
-#define DDRSS_CTL_51_DATA 0x08282628
+#define DDRSS_CTL_45_DATA 0x1E161104
+#define DDRSS_CTL_46_DATA 0x10012458
+#define DDRSS_CTL_47_DATA 0x1E161110
+#define DDRSS_CTL_48_DATA 0x10012458
+#define DDRSS_CTL_49_DATA 0x02030410
+#define DDRSS_CTL_50_DATA 0x2C040500
+#define DDRSS_CTL_51_DATA 0x082D2C2D
#define DDRSS_CTL_52_DATA 0x14000D0A
-#define DDRSS_CTL_53_DATA 0x03010A0A
-#define DDRSS_CTL_54_DATA 0x01010003
-#define DDRSS_CTL_55_DATA 0x044E4E08
-#define DDRSS_CTL_56_DATA 0x042B2B04
-#define DDRSS_CTL_57_DATA 0x00002B2B
+#define DDRSS_CTL_53_DATA 0x04010A0A
+#define DDRSS_CTL_54_DATA 0x01010004
+#define DDRSS_CTL_55_DATA 0x04585808
+#define DDRSS_CTL_56_DATA 0x04313104
+#define DDRSS_CTL_57_DATA 0x00003131
#define DDRSS_CTL_58_DATA 0x00010100
#define DDRSS_CTL_59_DATA 0x03010000
#define DDRSS_CTL_60_DATA 0x00000E08
#define DDRSS_CTL_61_DATA 0x000000BB
-#define DDRSS_CTL_62_DATA 0x0000020B
-#define DDRSS_CTL_63_DATA 0x00001C64
-#define DDRSS_CTL_64_DATA 0x0000020B
-#define DDRSS_CTL_65_DATA 0x00001C64
+#define DDRSS_CTL_62_DATA 0x00000256
+#define DDRSS_CTL_63_DATA 0x00002073
+#define DDRSS_CTL_64_DATA 0x00000256
+#define DDRSS_CTL_65_DATA 0x00002073
#define DDRSS_CTL_66_DATA 0x00000005
#define DDRSS_CTL_67_DATA 0x00030000
-#define DDRSS_CTL_68_DATA 0x00830010
-#define DDRSS_CTL_69_DATA 0x00830386
-#define DDRSS_CTL_70_DATA 0x00400386
+#define DDRSS_CTL_68_DATA 0x00950010
+#define DDRSS_CTL_69_DATA 0x00950408
+#define DDRSS_CTL_70_DATA 0x00400408
#define DDRSS_CTL_71_DATA 0x00120103
-#define DDRSS_CTL_72_DATA 0x000E0005
-#define DDRSS_CTL_73_DATA 0x2908000E
-#define DDRSS_CTL_74_DATA 0x05050129
+#define DDRSS_CTL_72_DATA 0x00100005
+#define DDRSS_CTL_73_DATA 0x2F080010
+#define DDRSS_CTL_74_DATA 0x0505012F
#define DDRSS_CTL_75_DATA 0x0401030A
-#define DDRSS_CTL_76_DATA 0x041B0E0A
-#define DDRSS_CTL_77_DATA 0x0E0A0401
-#define DDRSS_CTL_78_DATA 0x0001041B
+#define DDRSS_CTL_76_DATA 0x041E100B
+#define DDRSS_CTL_77_DATA 0x100B0401
+#define DDRSS_CTL_78_DATA 0x0001041E
#define DDRSS_CTL_79_DATA 0x000F000F
-#define DDRSS_CTL_80_DATA 0x02190219
-#define DDRSS_CTL_81_DATA 0x02190219
+#define DDRSS_CTL_80_DATA 0x02660266
+#define DDRSS_CTL_81_DATA 0x02660266
#define DDRSS_CTL_82_DATA 0x03050505
#define DDRSS_CTL_83_DATA 0x03010303
-#define DDRSS_CTL_84_DATA 0x1C0A0E0A
-#define DDRSS_CTL_85_DATA 0x04040E04
-#define DDRSS_CTL_86_DATA 0x1C0A0E0A
-#define DDRSS_CTL_87_DATA 0x04040E04
+#define DDRSS_CTL_84_DATA 0x200B100B
+#define DDRSS_CTL_85_DATA 0x04041004
+#define DDRSS_CTL_86_DATA 0x200B100B
+#define DDRSS_CTL_87_DATA 0x04041004
#define DDRSS_CTL_88_DATA 0x03010000
#define DDRSS_CTL_89_DATA 0x00010000
#define DDRSS_CTL_90_DATA 0x00000000
@@ -118,20 +118,20 @@
#define DDRSS_CTL_106_DATA 0x00002EC0
#define DDRSS_CTL_107_DATA 0x00000000
#define DDRSS_CTL_108_DATA 0x0000051D
-#define DDRSS_CTL_109_DATA 0x00071900
-#define DDRSS_CTL_110_DATA 0x00071900
-#define DDRSS_CTL_111_DATA 0x00071900
-#define DDRSS_CTL_112_DATA 0x00071900
-#define DDRSS_CTL_113_DATA 0x00071900
+#define DDRSS_CTL_109_DATA 0x00081CC0
+#define DDRSS_CTL_110_DATA 0x00081CC0
+#define DDRSS_CTL_111_DATA 0x00081CC0
+#define DDRSS_CTL_112_DATA 0x00081CC0
+#define DDRSS_CTL_113_DATA 0x00081CC0
#define DDRSS_CTL_114_DATA 0x00000000
-#define DDRSS_CTL_115_DATA 0x0000C6BC
-#define DDRSS_CTL_116_DATA 0x00071900
-#define DDRSS_CTL_117_DATA 0x00071900
-#define DDRSS_CTL_118_DATA 0x00071900
-#define DDRSS_CTL_119_DATA 0x00071900
-#define DDRSS_CTL_120_DATA 0x00071900
+#define DDRSS_CTL_115_DATA 0x0000E325
+#define DDRSS_CTL_116_DATA 0x00081CC0
+#define DDRSS_CTL_117_DATA 0x00081CC0
+#define DDRSS_CTL_118_DATA 0x00081CC0
+#define DDRSS_CTL_119_DATA 0x00081CC0
+#define DDRSS_CTL_120_DATA 0x00081CC0
#define DDRSS_CTL_121_DATA 0x00000000
-#define DDRSS_CTL_122_DATA 0x0000C6BC
+#define DDRSS_CTL_122_DATA 0x0000E325
#define DDRSS_CTL_123_DATA 0x00000000
#define DDRSS_CTL_124_DATA 0x00000000
#define DDRSS_CTL_125_DATA 0x00000000
@@ -140,8 +140,8 @@
#define DDRSS_CTL_128_DATA 0x00000000
#define DDRSS_CTL_129_DATA 0x00000000
#define DDRSS_CTL_130_DATA 0x00000000
-#define DDRSS_CTL_131_DATA 0x0A030500
-#define DDRSS_CTL_132_DATA 0x00040A04
+#define DDRSS_CTL_131_DATA 0x0B030500
+#define DDRSS_CTL_132_DATA 0x00040B04
#define DDRSS_CTL_133_DATA 0x0A090000
#define DDRSS_CTL_134_DATA 0x0A090701
#define DDRSS_CTL_135_DATA 0x0900000E
@@ -176,23 +176,23 @@
#define DDRSS_CTL_164_DATA 0x000A0000
#define DDRSS_CTL_165_DATA 0x000D0005
#define DDRSS_CTL_166_DATA 0x000D0404
-#define DDRSS_CTL_167_DATA 0x00BB0176
-#define DDRSS_CTL_168_DATA 0x0E0E01D3
-#define DDRSS_CTL_169_DATA 0x017601D3
-#define DDRSS_CTL_170_DATA 0x01D300BB
-#define DDRSS_CTL_171_DATA 0x01D30E0E
+#define DDRSS_CTL_167_DATA 0x00D601AB
+#define DDRSS_CTL_168_DATA 0x10100216
+#define DDRSS_CTL_169_DATA 0x01AB0216
+#define DDRSS_CTL_170_DATA 0x021600D6
+#define DDRSS_CTL_171_DATA 0x02161010
#define DDRSS_CTL_172_DATA 0x00000000
#define DDRSS_CTL_173_DATA 0x00000000
#define DDRSS_CTL_174_DATA 0x00000000
-#define DDRSS_CTL_175_DATA 0x36E40084
-#define DDRSS_CTL_176_DATA 0x330036E4
+#define DDRSS_CTL_175_DATA 0x3FF40084
+#define DDRSS_CTL_176_DATA 0x33003FF4
#define DDRSS_CTL_177_DATA 0x00003333
#define DDRSS_CTL_178_DATA 0x56000000
#define DDRSS_CTL_179_DATA 0x27270056
#define DDRSS_CTL_180_DATA 0x0F0F0000
#define DDRSS_CTL_181_DATA 0x00000000
#define DDRSS_CTL_182_DATA 0x00840606
-#define DDRSS_CTL_183_DATA 0x36E436E4
+#define DDRSS_CTL_183_DATA 0x3FF43FF4
#define DDRSS_CTL_184_DATA 0x33333300
#define DDRSS_CTL_185_DATA 0x00000000
#define DDRSS_CTL_186_DATA 0x00565600
@@ -270,12 +270,12 @@
#define DDRSS_CTL_258_DATA 0x00320040
#define DDRSS_CTL_259_DATA 0x00020008
#define DDRSS_CTL_260_DATA 0x00400100
-#define DDRSS_CTL_261_DATA 0x0038074A
+#define DDRSS_CTL_261_DATA 0x00400855
#define DDRSS_CTL_262_DATA 0x01000200
-#define DDRSS_CTL_263_DATA 0x074A0040
-#define DDRSS_CTL_264_DATA 0x00000038
-#define DDRSS_CTL_265_DATA 0x005E0003
-#define DDRSS_CTL_266_DATA 0x0100005E
+#define DDRSS_CTL_263_DATA 0x08550040
+#define DDRSS_CTL_264_DATA 0x00000040
+#define DDRSS_CTL_265_DATA 0x006B0003
+#define DDRSS_CTL_266_DATA 0x0100006B
#define DDRSS_CTL_267_DATA 0x00000000
#define DDRSS_CTL_268_DATA 0x01010000
#define DDRSS_CTL_269_DATA 0x00000202
@@ -327,15 +327,15 @@
#define DDRSS_CTL_315_DATA 0x01000101
#define DDRSS_CTL_316_DATA 0x01010001
#define DDRSS_CTL_317_DATA 0x00010101
-#define DDRSS_CTL_318_DATA 0x05090903
-#define DDRSS_CTL_319_DATA 0x0E081B1B
-#define DDRSS_CTL_320_DATA 0x0009030E
-#define DDRSS_CTL_321_DATA 0x0A0D030F
-#define DDRSS_CTL_322_DATA 0x0A0D0306
-#define DDRSS_CTL_323_DATA 0x0D090006
-#define DDRSS_CTL_324_DATA 0x0100000D
-#define DDRSS_CTL_325_DATA 0x07030701
-#define DDRSS_CTL_326_DATA 0x00000003
+#define DDRSS_CTL_318_DATA 0x050A0A03
+#define DDRSS_CTL_319_DATA 0x10081F1F
+#define DDRSS_CTL_320_DATA 0x00090310
+#define DDRSS_CTL_321_DATA 0x0B0C030F
+#define DDRSS_CTL_322_DATA 0x0B0C0306
+#define DDRSS_CTL_323_DATA 0x0C090006
+#define DDRSS_CTL_324_DATA 0x0100000C
+#define DDRSS_CTL_325_DATA 0x08040801
+#define DDRSS_CTL_326_DATA 0x00000004
#define DDRSS_CTL_327_DATA 0x00000000
#define DDRSS_CTL_328_DATA 0x00010000
#define DDRSS_CTL_329_DATA 0x00280D00
@@ -396,7 +396,7 @@
#define DDRSS_CTL_384_DATA 0x00000000
#define DDRSS_CTL_385_DATA 0x00000000
#define DDRSS_CTL_386_DATA 0x00000000
-#define DDRSS_CTL_387_DATA 0x37371B00
+#define DDRSS_CTL_387_DATA 0x3A3A1B00
#define DDRSS_CTL_388_DATA 0x000A0000
#define DDRSS_CTL_389_DATA 0x00000176
#define DDRSS_CTL_390_DATA 0x00000200
@@ -406,22 +406,22 @@
#define DDRSS_CTL_394_DATA 0x00000462
#define DDRSS_CTL_395_DATA 0x00000E9C
#define DDRSS_CTL_396_DATA 0x00000204
-#define DDRSS_CTL_397_DATA 0x000038C8
+#define DDRSS_CTL_397_DATA 0x000040E6
#define DDRSS_CTL_398_DATA 0x00000200
#define DDRSS_CTL_399_DATA 0x00000200
#define DDRSS_CTL_400_DATA 0x00000200
#define DDRSS_CTL_401_DATA 0x00000200
-#define DDRSS_CTL_402_DATA 0x0000AA58
-#define DDRSS_CTL_403_DATA 0x000237D0
-#define DDRSS_CTL_404_DATA 0x00000C12
-#define DDRSS_CTL_405_DATA 0x000038C8
+#define DDRSS_CTL_402_DATA 0x0000C2B2
+#define DDRSS_CTL_403_DATA 0x000288FC
+#define DDRSS_CTL_404_DATA 0x00000E15
+#define DDRSS_CTL_405_DATA 0x000040E6
#define DDRSS_CTL_406_DATA 0x00000200
#define DDRSS_CTL_407_DATA 0x00000200
#define DDRSS_CTL_408_DATA 0x00000200
#define DDRSS_CTL_409_DATA 0x00000200
-#define DDRSS_CTL_410_DATA 0x0000AA58
-#define DDRSS_CTL_411_DATA 0x000237D0
-#define DDRSS_CTL_412_DATA 0x02020C12
+#define DDRSS_CTL_410_DATA 0x0000C2B2
+#define DDRSS_CTL_411_DATA 0x000288FC
+#define DDRSS_CTL_412_DATA 0x02020E15
#define DDRSS_CTL_413_DATA 0x03030202
#define DDRSS_CTL_414_DATA 0x00000022
#define DDRSS_CTL_415_DATA 0x00000000
@@ -432,13 +432,13 @@
#define DDRSS_CTL_420_DATA 0x00000000
#define DDRSS_CTL_421_DATA 0x00030000
#define DDRSS_CTL_422_DATA 0x0006001E
-#define DDRSS_CTL_423_DATA 0x00190031
-#define DDRSS_CTL_424_DATA 0x00190031
+#define DDRSS_CTL_423_DATA 0x001B0033
+#define DDRSS_CTL_424_DATA 0x001B0033
#define DDRSS_CTL_425_DATA 0x00000000
#define DDRSS_CTL_426_DATA 0x00000000
#define DDRSS_CTL_427_DATA 0x02000000
#define DDRSS_CTL_428_DATA 0x01000404
-#define DDRSS_CTL_429_DATA 0x091A091A
+#define DDRSS_CTL_429_DATA 0x0B1E0B1E
#define DDRSS_CTL_430_DATA 0x00000105
#define DDRSS_CTL_431_DATA 0x00010101
#define DDRSS_CTL_432_DATA 0x00010101
@@ -447,8 +447,8 @@
#define DDRSS_CTL_435_DATA 0x02000201
#define DDRSS_CTL_436_DATA 0x02010000
#define DDRSS_CTL_437_DATA 0x00000200
-#define DDRSS_CTL_438_DATA 0x22060000
-#define DDRSS_CTL_439_DATA 0x00000122
+#define DDRSS_CTL_438_DATA 0x28060000
+#define DDRSS_CTL_439_DATA 0x00000128
#define DDRSS_CTL_440_DATA 0xFFFFFFFF
#define DDRSS_CTL_441_DATA 0xFFFFFFFF
#define DDRSS_CTL_442_DATA 0x00000000
@@ -515,7 +515,7 @@
#define DDRSS_PI_43_DATA 0x00000000
#define DDRSS_PI_44_DATA 0x00000000
#define DDRSS_PI_45_DATA 0x000F0F00
-#define DDRSS_PI_46_DATA 0x00000019
+#define DDRSS_PI_46_DATA 0x0000001B
#define DDRSS_PI_47_DATA 0x000007D0
#define DDRSS_PI_48_DATA 0x00000300
#define DDRSS_PI_49_DATA 0x00000000
@@ -535,13 +535,13 @@
#define DDRSS_PI_63_DATA 0x01000404
#define DDRSS_PI_64_DATA 0x00000000
#define DDRSS_PI_65_DATA 0x00000000
-#define DDRSS_PI_66_DATA 0x00000101
+#define DDRSS_PI_66_DATA 0x00000100
#define DDRSS_PI_67_DATA 0x0001010F
#define DDRSS_PI_68_DATA 0x00340000
#define DDRSS_PI_69_DATA 0x00000000
#define DDRSS_PI_70_DATA 0x00000000
-#define DDRSS_PI_71_DATA 0x00000000
-#define DDRSS_PI_72_DATA 0x01000000
+#define DDRSS_PI_71_DATA 0x0000FFFF
+#define DDRSS_PI_72_DATA 0x00000000
#define DDRSS_PI_73_DATA 0x00080100
#define DDRSS_PI_74_DATA 0x02000200
#define DDRSS_PI_75_DATA 0x01000100
@@ -632,18 +632,18 @@
#define DDRSS_PI_160_DATA 0x00000000
#define DDRSS_PI_161_DATA 0x00010000
#define DDRSS_PI_162_DATA 0x00000000
-#define DDRSS_PI_163_DATA 0x26260100
+#define DDRSS_PI_163_DATA 0x2B2B0100
#define DDRSS_PI_164_DATA 0x00000034
-#define DDRSS_PI_165_DATA 0x0000005E
-#define DDRSS_PI_166_DATA 0x0002005E
+#define DDRSS_PI_165_DATA 0x00000064
+#define DDRSS_PI_166_DATA 0x00020064
#define DDRSS_PI_167_DATA 0x02000200
-#define DDRSS_PI_168_DATA 0x40100C04
-#define DDRSS_PI_169_DATA 0x000E4010
+#define DDRSS_PI_168_DATA 0x48120C04
+#define DDRSS_PI_169_DATA 0x000E4812
#define DDRSS_PI_170_DATA 0x000000BB
-#define DDRSS_PI_171_DATA 0x0000020B
-#define DDRSS_PI_172_DATA 0x00001C64
-#define DDRSS_PI_173_DATA 0x0000020B
-#define DDRSS_PI_174_DATA 0x04001C64
+#define DDRSS_PI_171_DATA 0x00000256
+#define DDRSS_PI_172_DATA 0x00002073
+#define DDRSS_PI_173_DATA 0x00000256
+#define DDRSS_PI_174_DATA 0x04002073
#define DDRSS_PI_175_DATA 0x01010404
#define DDRSS_PI_176_DATA 0x00001501
#define DDRSS_PI_177_DATA 0x00150015
@@ -654,80 +654,80 @@
#define DDRSS_PI_182_DATA 0x00000101
#define DDRSS_PI_183_DATA 0x00000000
#define DDRSS_PI_184_DATA 0x00000000
-#define DDRSS_PI_185_DATA 0x12040000
-#define DDRSS_PI_186_DATA 0x0C0C0212
+#define DDRSS_PI_185_DATA 0x15040000
+#define DDRSS_PI_186_DATA 0x0E0E0215
#define DDRSS_PI_187_DATA 0x00040402
#define DDRSS_PI_188_DATA 0x000C8034
-#define DDRSS_PI_189_DATA 0x001F0047
-#define DDRSS_PI_190_DATA 0x001F0047
+#define DDRSS_PI_189_DATA 0x00218049
+#define DDRSS_PI_190_DATA 0x00218049
#define DDRSS_PI_191_DATA 0x01010101
-#define DDRSS_PI_192_DATA 0x0003000D
-#define DDRSS_PI_193_DATA 0x000301D3
-#define DDRSS_PI_194_DATA 0x010001D3
+#define DDRSS_PI_192_DATA 0x0004000D
+#define DDRSS_PI_193_DATA 0x00040216
+#define DDRSS_PI_194_DATA 0x01000216
#define DDRSS_PI_195_DATA 0x000E000E
-#define DDRSS_PI_196_DATA 0x01D40100
-#define DDRSS_PI_197_DATA 0x010001D4
-#define DDRSS_PI_198_DATA 0x01D401D4
+#define DDRSS_PI_196_DATA 0x02170100
+#define DDRSS_PI_197_DATA 0x01000217
+#define DDRSS_PI_198_DATA 0x02170217
#define DDRSS_PI_199_DATA 0x32103200
#define DDRSS_PI_200_DATA 0x01013210
#define DDRSS_PI_201_DATA 0x0A070601
-#define DDRSS_PI_202_DATA 0x1C11090D
-#define DDRSS_PI_203_DATA 0x1C110913
-#define DDRSS_PI_204_DATA 0x0000C013
+#define DDRSS_PI_202_DATA 0x1F130A0D
+#define DDRSS_PI_203_DATA 0x1F130A14
+#define DDRSS_PI_204_DATA 0x0000C014
#define DDRSS_PI_205_DATA 0x00C01000
#define DDRSS_PI_206_DATA 0x00C01000
#define DDRSS_PI_207_DATA 0x00021000
-#define DDRSS_PI_208_DATA 0x0021000D
-#define DDRSS_PI_209_DATA 0x002101D3
-#define DDRSS_PI_210_DATA 0x001101D3
+#define DDRSS_PI_208_DATA 0x0024000D
+#define DDRSS_PI_209_DATA 0x00240216
+#define DDRSS_PI_210_DATA 0x00110216
#define DDRSS_PI_211_DATA 0x32000056
-#define DDRSS_PI_212_DATA 0x00000101
-#define DDRSS_PI_213_DATA 0x005A0035
-#define DDRSS_PI_214_DATA 0x01013212
-#define DDRSS_PI_215_DATA 0x00003500
-#define DDRSS_PI_216_DATA 0x3212005A
-#define DDRSS_PI_217_DATA 0x09000101
+#define DDRSS_PI_212_DATA 0x00000301
+#define DDRSS_PI_213_DATA 0x005B003A
+#define DDRSS_PI_214_DATA 0x03013212
+#define DDRSS_PI_215_DATA 0x00003A00
+#define DDRSS_PI_216_DATA 0x3212005B
+#define DDRSS_PI_217_DATA 0x09000301
#define DDRSS_PI_218_DATA 0x04010504
#define DDRSS_PI_219_DATA 0x0400062B
#define DDRSS_PI_220_DATA 0x0A032001
-#define DDRSS_PI_221_DATA 0x262B0F0A
-#define DDRSS_PI_222_DATA 0x00002819
-#define DDRSS_PI_223_DATA 0x5400E638
-#define DDRSS_PI_224_DATA 0x1B1C2007
-#define DDRSS_PI_225_DATA 0x262B0F13
-#define DDRSS_PI_226_DATA 0x00002819
-#define DDRSS_PI_227_DATA 0x5400E638
-#define DDRSS_PI_228_DATA 0x1B1C2007
-#define DDRSS_PI_229_DATA 0x00017613
+#define DDRSS_PI_221_DATA 0x2C31110A
+#define DDRSS_PI_222_DATA 0x00002D1C
+#define DDRSS_PI_223_DATA 0x6001071C
+#define DDRSS_PI_224_DATA 0x1E202008
+#define DDRSS_PI_225_DATA 0x2C311116
+#define DDRSS_PI_226_DATA 0x00002D1C
+#define DDRSS_PI_227_DATA 0x6001071C
+#define DDRSS_PI_228_DATA 0x1E202008
+#define DDRSS_PI_229_DATA 0x00017616
#define DDRSS_PI_230_DATA 0x00000E9C
-#define DDRSS_PI_231_DATA 0x000038C8
-#define DDRSS_PI_232_DATA 0x000237D0
-#define DDRSS_PI_233_DATA 0x000038C8
-#define DDRSS_PI_234_DATA 0x000237D0
-#define DDRSS_PI_235_DATA 0x0219000F
-#define DDRSS_PI_236_DATA 0x03030219
+#define DDRSS_PI_231_DATA 0x000040E6
+#define DDRSS_PI_232_DATA 0x000288FC
+#define DDRSS_PI_233_DATA 0x000040E6
+#define DDRSS_PI_234_DATA 0x000288FC
+#define DDRSS_PI_235_DATA 0x0266000F
+#define DDRSS_PI_236_DATA 0x03030266
#define DDRSS_PI_237_DATA 0x00271003
#define DDRSS_PI_238_DATA 0x000186A0
#define DDRSS_PI_239_DATA 0x00000005
#define DDRSS_PI_240_DATA 0x00000064
#define DDRSS_PI_241_DATA 0x0000000F
-#define DDRSS_PI_242_DATA 0x0005B18F
+#define DDRSS_PI_242_DATA 0x000681C8
#define DDRSS_PI_243_DATA 0x000186A0
#define DDRSS_PI_244_DATA 0x00000005
-#define DDRSS_PI_245_DATA 0x00000E94
-#define DDRSS_PI_246_DATA 0x00000219
-#define DDRSS_PI_247_DATA 0x0005B18F
+#define DDRSS_PI_245_DATA 0x000010A9
+#define DDRSS_PI_246_DATA 0x00000266
+#define DDRSS_PI_247_DATA 0x000681C8
#define DDRSS_PI_248_DATA 0x000186A0
#define DDRSS_PI_249_DATA 0x00000005
-#define DDRSS_PI_250_DATA 0x00000E94
-#define DDRSS_PI_251_DATA 0x01000219
+#define DDRSS_PI_250_DATA 0x000010A9
+#define DDRSS_PI_251_DATA 0x01000266
#define DDRSS_PI_252_DATA 0x00320040
#define DDRSS_PI_253_DATA 0x00010008
-#define DDRSS_PI_254_DATA 0x074A0040
-#define DDRSS_PI_255_DATA 0x00010038
-#define DDRSS_PI_256_DATA 0x074A0040
-#define DDRSS_PI_257_DATA 0x00000338
-#define DDRSS_PI_258_DATA 0x005E005E
+#define DDRSS_PI_254_DATA 0x08550040
+#define DDRSS_PI_255_DATA 0x00010040
+#define DDRSS_PI_256_DATA 0x08550040
+#define DDRSS_PI_257_DATA 0x00000340
+#define DDRSS_PI_258_DATA 0x006B006B
#define DDRSS_PI_259_DATA 0x00040404
#define DDRSS_PI_260_DATA 0x00000055
#define DDRSS_PI_261_DATA 0x55003C5A
@@ -746,27 +746,27 @@
#define DDRSS_PI_274_DATA 0x00000000
#define DDRSS_PI_275_DATA 0x00330084
#define DDRSS_PI_276_DATA 0x00160000
-#define DDRSS_PI_277_DATA 0x563336E4
+#define DDRSS_PI_277_DATA 0x56333FF4
#define DDRSS_PI_278_DATA 0x00160F27
-#define DDRSS_PI_279_DATA 0x563336E4
+#define DDRSS_PI_279_DATA 0x56333FF4
#define DDRSS_PI_280_DATA 0x00160F27
#define DDRSS_PI_281_DATA 0x00330084
#define DDRSS_PI_282_DATA 0x00160000
-#define DDRSS_PI_283_DATA 0x563336E4
+#define DDRSS_PI_283_DATA 0x56333FF4
#define DDRSS_PI_284_DATA 0x00160F27
-#define DDRSS_PI_285_DATA 0x563336E4
+#define DDRSS_PI_285_DATA 0x56333FF4
#define DDRSS_PI_286_DATA 0x00160F27
#define DDRSS_PI_287_DATA 0x00330084
#define DDRSS_PI_288_DATA 0x00160000
-#define DDRSS_PI_289_DATA 0x563336E4
+#define DDRSS_PI_289_DATA 0x56333FF4
#define DDRSS_PI_290_DATA 0x00160F27
-#define DDRSS_PI_291_DATA 0x563336E4
+#define DDRSS_PI_291_DATA 0x56333FF4
#define DDRSS_PI_292_DATA 0x00160F27
#define DDRSS_PI_293_DATA 0x00330084
#define DDRSS_PI_294_DATA 0x00160000
-#define DDRSS_PI_295_DATA 0x563336E4
+#define DDRSS_PI_295_DATA 0x56333FF4
#define DDRSS_PI_296_DATA 0x00160F27
-#define DDRSS_PI_297_DATA 0x563336E4
+#define DDRSS_PI_297_DATA 0x56333FF4
#define DDRSS_PI_298_DATA 0x00160F27
#define DDRSS_PI_299_DATA 0x00000000
@@ -787,7 +787,7 @@
#define DDRSS_PHY_14_DATA 0x060100CC
#define DDRSS_PHY_15_DATA 0x00030066
#define DDRSS_PHY_16_DATA 0x00000000
-#define DDRSS_PHY_17_DATA 0x00000001
+#define DDRSS_PHY_17_DATA 0x00000301
#define DDRSS_PHY_18_DATA 0x0000AAAA
#define DDRSS_PHY_19_DATA 0x00005555
#define DDRSS_PHY_20_DATA 0x0000B5B5
@@ -803,7 +803,7 @@
#define DDRSS_PHY_30_DATA 0x0F000000
#define DDRSS_PHY_31_DATA 0x00000F0F
#define DDRSS_PHY_32_DATA 0x10200000
-#define DDRSS_PHY_33_DATA 0x0C002004
+#define DDRSS_PHY_33_DATA 0x0C002007
#define DDRSS_PHY_34_DATA 0x00000000
#define DDRSS_PHY_35_DATA 0x00000000
#define DDRSS_PHY_36_DATA 0x55555555
@@ -855,35 +855,35 @@
#define DDRSS_PHY_82_DATA 0x00000000
#define DDRSS_PHY_83_DATA 0x00000100
#define DDRSS_PHY_84_DATA 0x01CC0C01
-#define DDRSS_PHY_85_DATA 0x0003CC0C
+#define DDRSS_PHY_85_DATA 0x1003CC0C
#define DDRSS_PHY_86_DATA 0x20000140
#define DDRSS_PHY_87_DATA 0x07FF0200
#define DDRSS_PHY_88_DATA 0x0000DD01
#define DDRSS_PHY_89_DATA 0x10100303
#define DDRSS_PHY_90_DATA 0x10101010
#define DDRSS_PHY_91_DATA 0x10101010
-#define DDRSS_PHY_92_DATA 0x00041010
+#define DDRSS_PHY_92_DATA 0x00021010
#define DDRSS_PHY_93_DATA 0x00100010
#define DDRSS_PHY_94_DATA 0x00100010
#define DDRSS_PHY_95_DATA 0x00100010
#define DDRSS_PHY_96_DATA 0x00100010
#define DDRSS_PHY_97_DATA 0x00050010
#define DDRSS_PHY_98_DATA 0x51517041
-#define DDRSS_PHY_99_DATA 0x31C06000
+#define DDRSS_PHY_99_DATA 0x31C06001
#define DDRSS_PHY_100_DATA 0x07AB0340
#define DDRSS_PHY_101_DATA 0x00C0C001
-#define DDRSS_PHY_102_DATA 0x0D0C0001
+#define DDRSS_PHY_102_DATA 0x0E0D0001
#define DDRSS_PHY_103_DATA 0x10001000
-#define DDRSS_PHY_104_DATA 0x0C063E42
-#define DDRSS_PHY_105_DATA 0x0F0C3201
+#define DDRSS_PHY_104_DATA 0x0C083E42
+#define DDRSS_PHY_105_DATA 0x0F0C3701
#define DDRSS_PHY_106_DATA 0x01000140
#define DDRSS_PHY_107_DATA 0x0C000420
-#define DDRSS_PHY_108_DATA 0x000002DD
+#define DDRSS_PHY_108_DATA 0x00000322
#define DDRSS_PHY_109_DATA 0x0A0000D0
#define DDRSS_PHY_110_DATA 0x00030200
#define DDRSS_PHY_111_DATA 0x02800000
#define DDRSS_PHY_112_DATA 0x80800000
-#define DDRSS_PHY_113_DATA 0x000D2010
+#define DDRSS_PHY_113_DATA 0x000E2010
#define DDRSS_PHY_114_DATA 0x76543210
#define DDRSS_PHY_115_DATA 0x00000008
#define DDRSS_PHY_116_DATA 0x02800280
@@ -900,13 +900,13 @@
#define DDRSS_PHY_127_DATA 0x00A000A0
#define DDRSS_PHY_128_DATA 0x00A000A0
#define DDRSS_PHY_129_DATA 0x00A000A0
-#define DDRSS_PHY_130_DATA 0x006D00A0
+#define DDRSS_PHY_130_DATA 0x01C200A0
#define DDRSS_PHY_131_DATA 0x01A00005
#define DDRSS_PHY_132_DATA 0x00000000
#define DDRSS_PHY_133_DATA 0x00000000
#define DDRSS_PHY_134_DATA 0x00080200
#define DDRSS_PHY_135_DATA 0x00000000
-#define DDRSS_PHY_136_DATA 0x20202020
+#define DDRSS_PHY_136_DATA 0x20202000
#define DDRSS_PHY_137_DATA 0x20202020
#define DDRSS_PHY_138_DATA 0xF0F02020
#define DDRSS_PHY_139_DATA 0x00000000
@@ -1043,7 +1043,7 @@
#define DDRSS_PHY_270_DATA 0x060100CC
#define DDRSS_PHY_271_DATA 0x00030066
#define DDRSS_PHY_272_DATA 0x00000000
-#define DDRSS_PHY_273_DATA 0x00000001
+#define DDRSS_PHY_273_DATA 0x00000301
#define DDRSS_PHY_274_DATA 0x0000AAAA
#define DDRSS_PHY_275_DATA 0x00005555
#define DDRSS_PHY_276_DATA 0x0000B5B5
@@ -1059,7 +1059,7 @@
#define DDRSS_PHY_286_DATA 0x0F000000
#define DDRSS_PHY_287_DATA 0x00000F0F
#define DDRSS_PHY_288_DATA 0x10200000
-#define DDRSS_PHY_289_DATA 0x0C002004
+#define DDRSS_PHY_289_DATA 0x0C002007
#define DDRSS_PHY_290_DATA 0x00000000
#define DDRSS_PHY_291_DATA 0x00000000
#define DDRSS_PHY_292_DATA 0x55555555
@@ -1111,35 +1111,35 @@
#define DDRSS_PHY_338_DATA 0x00000000
#define DDRSS_PHY_339_DATA 0x00000100
#define DDRSS_PHY_340_DATA 0x01CC0C01
-#define DDRSS_PHY_341_DATA 0x0003CC0C
+#define DDRSS_PHY_341_DATA 0x1003CC0C
#define DDRSS_PHY_342_DATA 0x20000140
#define DDRSS_PHY_343_DATA 0x07FF0200
#define DDRSS_PHY_344_DATA 0x0000DD01
#define DDRSS_PHY_345_DATA 0x10100303
#define DDRSS_PHY_346_DATA 0x10101010
#define DDRSS_PHY_347_DATA 0x10101010
-#define DDRSS_PHY_348_DATA 0x00041010
+#define DDRSS_PHY_348_DATA 0x00021010
#define DDRSS_PHY_349_DATA 0x00100010
#define DDRSS_PHY_350_DATA 0x00100010
#define DDRSS_PHY_351_DATA 0x00100010
#define DDRSS_PHY_352_DATA 0x00100010
#define DDRSS_PHY_353_DATA 0x00050010
#define DDRSS_PHY_354_DATA 0x51517041
-#define DDRSS_PHY_355_DATA 0x31C06000
+#define DDRSS_PHY_355_DATA 0x31C06001
#define DDRSS_PHY_356_DATA 0x07AB0340
#define DDRSS_PHY_357_DATA 0x00C0C001
-#define DDRSS_PHY_358_DATA 0x0D0C0001
+#define DDRSS_PHY_358_DATA 0x0E0D0001
#define DDRSS_PHY_359_DATA 0x10001000
-#define DDRSS_PHY_360_DATA 0x0C063E42
-#define DDRSS_PHY_361_DATA 0x0F0C3201
+#define DDRSS_PHY_360_DATA 0x0C083E42
+#define DDRSS_PHY_361_DATA 0x0F0C3701
#define DDRSS_PHY_362_DATA 0x01000140
#define DDRSS_PHY_363_DATA 0x0C000420
-#define DDRSS_PHY_364_DATA 0x000002DD
+#define DDRSS_PHY_364_DATA 0x00000322
#define DDRSS_PHY_365_DATA 0x0A0000D0
#define DDRSS_PHY_366_DATA 0x00030200
#define DDRSS_PHY_367_DATA 0x02800000
#define DDRSS_PHY_368_DATA 0x80800000
-#define DDRSS_PHY_369_DATA 0x000D2010
+#define DDRSS_PHY_369_DATA 0x000E2010
#define DDRSS_PHY_370_DATA 0x76543210
#define DDRSS_PHY_371_DATA 0x00000008
#define DDRSS_PHY_372_DATA 0x02800280
@@ -1156,13 +1156,13 @@
#define DDRSS_PHY_383_DATA 0x00A000A0
#define DDRSS_PHY_384_DATA 0x00A000A0
#define DDRSS_PHY_385_DATA 0x00A000A0
-#define DDRSS_PHY_386_DATA 0x006D00A0
+#define DDRSS_PHY_386_DATA 0x01C200A0
#define DDRSS_PHY_387_DATA 0x01A00005
#define DDRSS_PHY_388_DATA 0x00000000
#define DDRSS_PHY_389_DATA 0x00000000
#define DDRSS_PHY_390_DATA 0x00080200
#define DDRSS_PHY_391_DATA 0x00000000
-#define DDRSS_PHY_392_DATA 0x20202020
+#define DDRSS_PHY_392_DATA 0x20202000
#define DDRSS_PHY_393_DATA 0x20202020
#define DDRSS_PHY_394_DATA 0xF0F02020
#define DDRSS_PHY_395_DATA 0x00000000
@@ -1299,7 +1299,7 @@
#define DDRSS_PHY_526_DATA 0x060100CC
#define DDRSS_PHY_527_DATA 0x00030066
#define DDRSS_PHY_528_DATA 0x00000000
-#define DDRSS_PHY_529_DATA 0x00000001
+#define DDRSS_PHY_529_DATA 0x00000301
#define DDRSS_PHY_530_DATA 0x0000AAAA
#define DDRSS_PHY_531_DATA 0x00005555
#define DDRSS_PHY_532_DATA 0x0000B5B5
@@ -1315,7 +1315,7 @@
#define DDRSS_PHY_542_DATA 0x0F000000
#define DDRSS_PHY_543_DATA 0x00000F0F
#define DDRSS_PHY_544_DATA 0x10200000
-#define DDRSS_PHY_545_DATA 0x0C002004
+#define DDRSS_PHY_545_DATA 0x0C002007
#define DDRSS_PHY_546_DATA 0x00000000
#define DDRSS_PHY_547_DATA 0x00000000
#define DDRSS_PHY_548_DATA 0x55555555
@@ -1367,35 +1367,35 @@
#define DDRSS_PHY_594_DATA 0x00000000
#define DDRSS_PHY_595_DATA 0x00000100
#define DDRSS_PHY_596_DATA 0x01CC0C01
-#define DDRSS_PHY_597_DATA 0x0003CC0C
+#define DDRSS_PHY_597_DATA 0x1003CC0C
#define DDRSS_PHY_598_DATA 0x20000140
#define DDRSS_PHY_599_DATA 0x07FF0200
#define DDRSS_PHY_600_DATA 0x0000DD01
#define DDRSS_PHY_601_DATA 0x10100303
#define DDRSS_PHY_602_DATA 0x10101010
#define DDRSS_PHY_603_DATA 0x10101010
-#define DDRSS_PHY_604_DATA 0x00041010
+#define DDRSS_PHY_604_DATA 0x00021010
#define DDRSS_PHY_605_DATA 0x00100010
#define DDRSS_PHY_606_DATA 0x00100010
#define DDRSS_PHY_607_DATA 0x00100010
#define DDRSS_PHY_608_DATA 0x00100010
#define DDRSS_PHY_609_DATA 0x00050010
#define DDRSS_PHY_610_DATA 0x51517041
-#define DDRSS_PHY_611_DATA 0x31C06000
+#define DDRSS_PHY_611_DATA 0x31C06001
#define DDRSS_PHY_612_DATA 0x07AB0340
#define DDRSS_PHY_613_DATA 0x00C0C001
-#define DDRSS_PHY_614_DATA 0x0D0C0001
+#define DDRSS_PHY_614_DATA 0x0E0D0001
#define DDRSS_PHY_615_DATA 0x10001000
-#define DDRSS_PHY_616_DATA 0x0C063E42
-#define DDRSS_PHY_617_DATA 0x0F0C3201
+#define DDRSS_PHY_616_DATA 0x0C083E42
+#define DDRSS_PHY_617_DATA 0x0F0C3701
#define DDRSS_PHY_618_DATA 0x01000140
#define DDRSS_PHY_619_DATA 0x0C000420
-#define DDRSS_PHY_620_DATA 0x000002DD
+#define DDRSS_PHY_620_DATA 0x00000322
#define DDRSS_PHY_621_DATA 0x0A0000D0
#define DDRSS_PHY_622_DATA 0x00030200
#define DDRSS_PHY_623_DATA 0x02800000
#define DDRSS_PHY_624_DATA 0x80800000
-#define DDRSS_PHY_625_DATA 0x000D2010
+#define DDRSS_PHY_625_DATA 0x000E2010
#define DDRSS_PHY_626_DATA 0x76543210
#define DDRSS_PHY_627_DATA 0x00000008
#define DDRSS_PHY_628_DATA 0x02800280
@@ -1412,13 +1412,13 @@
#define DDRSS_PHY_639_DATA 0x00A000A0
#define DDRSS_PHY_640_DATA 0x00A000A0
#define DDRSS_PHY_641_DATA 0x00A000A0
-#define DDRSS_PHY_642_DATA 0x006D00A0
+#define DDRSS_PHY_642_DATA 0x01C200A0
#define DDRSS_PHY_643_DATA 0x01A00005
#define DDRSS_PHY_644_DATA 0x00000000
#define DDRSS_PHY_645_DATA 0x00000000
#define DDRSS_PHY_646_DATA 0x00080200
#define DDRSS_PHY_647_DATA 0x00000000
-#define DDRSS_PHY_648_DATA 0x20202020
+#define DDRSS_PHY_648_DATA 0x20202000
#define DDRSS_PHY_649_DATA 0x20202020
#define DDRSS_PHY_650_DATA 0xF0F02020
#define DDRSS_PHY_651_DATA 0x00000000
@@ -1555,7 +1555,7 @@
#define DDRSS_PHY_782_DATA 0x060100CC
#define DDRSS_PHY_783_DATA 0x00030066
#define DDRSS_PHY_784_DATA 0x00000000
-#define DDRSS_PHY_785_DATA 0x00000001
+#define DDRSS_PHY_785_DATA 0x00000301
#define DDRSS_PHY_786_DATA 0x0000AAAA
#define DDRSS_PHY_787_DATA 0x00005555
#define DDRSS_PHY_788_DATA 0x0000B5B5
@@ -1571,7 +1571,7 @@
#define DDRSS_PHY_798_DATA 0x0F000000
#define DDRSS_PHY_799_DATA 0x00000F0F
#define DDRSS_PHY_800_DATA 0x10200000
-#define DDRSS_PHY_801_DATA 0x0C002004
+#define DDRSS_PHY_801_DATA 0x0C002007
#define DDRSS_PHY_802_DATA 0x00000000
#define DDRSS_PHY_803_DATA 0x00000000
#define DDRSS_PHY_804_DATA 0x55555555
@@ -1623,35 +1623,35 @@
#define DDRSS_PHY_850_DATA 0x00000000
#define DDRSS_PHY_851_DATA 0x00000100
#define DDRSS_PHY_852_DATA 0x01CC0C01
-#define DDRSS_PHY_853_DATA 0x0003CC0C
+#define DDRSS_PHY_853_DATA 0x1003CC0C
#define DDRSS_PHY_854_DATA 0x20000140
#define DDRSS_PHY_855_DATA 0x07FF0200
#define DDRSS_PHY_856_DATA 0x0000DD01
#define DDRSS_PHY_857_DATA 0x10100303
#define DDRSS_PHY_858_DATA 0x10101010
#define DDRSS_PHY_859_DATA 0x10101010
-#define DDRSS_PHY_860_DATA 0x00041010
+#define DDRSS_PHY_860_DATA 0x00021010
#define DDRSS_PHY_861_DATA 0x00100010
#define DDRSS_PHY_862_DATA 0x00100010
#define DDRSS_PHY_863_DATA 0x00100010
#define DDRSS_PHY_864_DATA 0x00100010
#define DDRSS_PHY_865_DATA 0x00050010
#define DDRSS_PHY_866_DATA 0x51517041
-#define DDRSS_PHY_867_DATA 0x31C06000
+#define DDRSS_PHY_867_DATA 0x31C06001
#define DDRSS_PHY_868_DATA 0x07AB0340
#define DDRSS_PHY_869_DATA 0x00C0C001
-#define DDRSS_PHY_870_DATA 0x0D0C0001
+#define DDRSS_PHY_870_DATA 0x0E0D0001
#define DDRSS_PHY_871_DATA 0x10001000
-#define DDRSS_PHY_872_DATA 0x0C063E42
-#define DDRSS_PHY_873_DATA 0x0F0C3201
+#define DDRSS_PHY_872_DATA 0x0C083E42
+#define DDRSS_PHY_873_DATA 0x0F0C3701
#define DDRSS_PHY_874_DATA 0x01000140
#define DDRSS_PHY_875_DATA 0x0C000420
-#define DDRSS_PHY_876_DATA 0x000002DD
+#define DDRSS_PHY_876_DATA 0x00000322
#define DDRSS_PHY_877_DATA 0x0A0000D0
#define DDRSS_PHY_878_DATA 0x00030200
#define DDRSS_PHY_879_DATA 0x02800000
#define DDRSS_PHY_880_DATA 0x80800000
-#define DDRSS_PHY_881_DATA 0x000D2010
+#define DDRSS_PHY_881_DATA 0x000E2010
#define DDRSS_PHY_882_DATA 0x76543210
#define DDRSS_PHY_883_DATA 0x00000008
#define DDRSS_PHY_884_DATA 0x02800280
@@ -1668,13 +1668,13 @@
#define DDRSS_PHY_895_DATA 0x00A000A0
#define DDRSS_PHY_896_DATA 0x00A000A0
#define DDRSS_PHY_897_DATA 0x00A000A0
-#define DDRSS_PHY_898_DATA 0x006D00A0
+#define DDRSS_PHY_898_DATA 0x01C200A0
#define DDRSS_PHY_899_DATA 0x01A00005
#define DDRSS_PHY_900_DATA 0x00000000
#define DDRSS_PHY_901_DATA 0x00000000
#define DDRSS_PHY_902_DATA 0x00080200
#define DDRSS_PHY_903_DATA 0x00000000
-#define DDRSS_PHY_904_DATA 0x20202020
+#define DDRSS_PHY_904_DATA 0x20202000
#define DDRSS_PHY_905_DATA 0x20202020
#define DDRSS_PHY_906_DATA 0xF0F02020
#define DDRSS_PHY_907_DATA 0x00000000
@@ -1834,7 +1834,7 @@
#define DDRSS_PHY_1061_DATA 0x00000000
#define DDRSS_PHY_1062_DATA 0x00000000
#define DDRSS_PHY_1063_DATA 0x00000000
-#define DDRSS_PHY_1064_DATA 0x000505FF
+#define DDRSS_PHY_1064_DATA 0x000305FF
#define DDRSS_PHY_1065_DATA 0x00030000
#define DDRSS_PHY_1066_DATA 0x00000300
#define DDRSS_PHY_1067_DATA 0x00000300
@@ -2163,8 +2163,8 @@
#define DDRSS_PHY_1390_DATA 0x00000000
#define DDRSS_PHY_1391_DATA 0x00000000
#define DDRSS_PHY_1392_DATA 0x00000000
-#define DDRSS_PHY_1393_DATA 0x0001F7C5
-#define DDRSS_PHY_1394_DATA 0x00000005
+#define DDRSS_PHY_1393_DATA 0x0001F7C0
+#define DDRSS_PHY_1394_DATA 0x00000003
#define DDRSS_PHY_1395_DATA 0x00000000
#define DDRSS_PHY_1396_DATA 0x00001142
#define DDRSS_PHY_1397_DATA 0x010207AB
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 2dde65d968..4cfaf8ca3c 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -6,7 +6,7 @@
/dts-v1/;
#include "k3-j721e-som-p0.dtsi"
-#include "k3-j721e-ddr-evm-lp4-3733.dtsi"
+#include "k3-j721e-ddr-evm-lp4-4266.dtsi"
#include "k3-j721e-ddr.dtsi"
/ {
--
2.17.1
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