[PATCH v2] imx: Add support for Ronetix's i.MX7-CM board.
Stefano Babic
sbabic at denx.de
Sun Dec 6 14:51:52 CET 2020
Hi Ilko,
your patch is since a long while in the list. I have merged it a couple
of times but I went back - sorry to not communicate this before.
Your patch create a DCD for the board - but we have full support for
i.MX6 and i.MX to set dinamically the DDR controller in SPL, see
mx7_dram_cfg(), and this makes board/ronetix/imx7-cm/imximage.cfg
superfluous. Do you have evaluated to switch to SPL instead of
hard-coding the DCD into u-boot.imx ?
Best regards,
Stefano Babic
On 13.07.20 16:00, Ilko Iliev wrote:
> Supported peripherals: ETH, SD, eMMC, USB, I2C EEPROM, PMIC, QSPI Nor
> Flash.
>
> U-Boot 2020.07-00611-g1fc3bcb2ee-dirty (Jul 13 2020 - 15:25:49 +0200)
>
> CPU: Freescale i.MX7D rev1.3 1000 MHz (running at 792 MHz)
> CPU: Commercial temperature grade (0C to 95C) at 39C
> Reset cause: POR
> Model: Ronetix i.MX7-CM Board
> Board: i.MX7-CM in non-secure mode
> DRAM: 512 MiB
> PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
> MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
> Loading Environment from MMC... OK
> In: serial
> Out: serial
> Err: serial
> Net: eth0: ethernet at 30be0000
> Hit any key to stop autoboot: 0
>
> Signed-off-by: Ilko Iliev <iliev at ronetix.at>
>
> Changes for v2:
> - support for i.MX7-CM v2.0
> - applicable to the current master branch
> ---
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/imx7-cm.dts | 674 +++++++++++++++++++++++++++++
> arch/arm/mach-imx/mx7/Kconfig | 10 +-
> board/ronetix/imx7-cm/Kconfig | 12 +
> board/ronetix/imx7-cm/MAINTAINERS | 6 +
> board/ronetix/imx7-cm/Makefile | 4 +
> board/ronetix/imx7-cm/imx7-cm.c | 210 +++++++++
> board/ronetix/imx7-cm/imximage.cfg | 104 +++++
> configs/imx7_cm_defconfig | 97 +++++
> include/configs/imx7-cm.h | 157 +++++++
> 10 files changed, 1275 insertions(+), 2 deletions(-)
> create mode 100644 arch/arm/dts/imx7-cm.dts
> create mode 100644 board/ronetix/imx7-cm/Kconfig
> create mode 100644 board/ronetix/imx7-cm/MAINTAINERS
> create mode 100644 board/ronetix/imx7-cm/Makefile
> create mode 100644 board/ronetix/imx7-cm/imx7-cm.c
> create mode 100644 board/ronetix/imx7-cm/imximage.cfg
> create mode 100644 configs/imx7_cm_defconfig
> create mode 100644 include/configs/imx7-cm.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index d839cb49b3..7a134190e5 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -730,7 +730,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
> imx7s-warp.dtb \
> imx7d-meerkat96.dtb \
> imx7d-pico-pi.dtb \
> - imx7d-pico-hobbit.dtb
> + imx7d-pico-hobbit.dtb \
> + imx7-cm.dtb
>
>
> dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
> diff --git a/arch/arm/dts/imx7-cm.dts b/arch/arm/dts/imx7-cm.dts
> new file mode 100644
> index 0000000000..1938a1829d
> --- /dev/null
> +++ b/arch/arm/dts/imx7-cm.dts
> @@ -0,0 +1,674 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2017 NXP
> + */
> +
> +/dts-v1/;
> +
> +#include "imx7d.dtsi"
> +
> +/ {
> + model = "Ronetix i.MX7-CM Board";
> + compatible = "fsl,imx7d-sdb", "fsl,imx7d";
> +
> + chosen {
> + stdout-path = &uart1;
> + };
> +
> + memory at 80000000 {
> + device_type = "memory";
> + reg = <0x80000000 0x80000000>;
> + };
> +
> + reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
> + compatible = "regulator-fixed";
> + regulator-name = "usb_otg1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
> + compatible = "regulator-fixed";
> + regulator-name = "usb_otg2_vbus";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_vref_1v8: regulator-vref-1v8 {
> + compatible = "regulator-fixed";
> + regulator-name = "vref-1v8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + reg_sd1_vmmc: regulator at 3 {
> + compatible = "regulator-fixed";
> + regulator-name = "VDD_SD1";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
> + startup-delay-us = <200000>;
> + enable-active-high;
> + };
> +
> + reg_sd2_vmmc: regulator at 4 {
> + compatible = "regulator-fixed";
> + regulator-name = "VDD_SD2";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sd2_vmmc_reg>;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
> + startup-delay-us = <200000>;
> + enable-active-high;
> + };
> +
> + reg_can2_3v3: regulator-can2-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "can2-3v3";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2_reg>;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
> + };
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pwm1 0 5000000 0>;
> + brightness-levels = <0 4 8 16 32 64 128 255>;
> + default-brightness-level = <6>;
> + status = "okay";
> + };
> +};
> +
> +&adc1 {
> + vref-supply = <®_vref_1v8>;
> + status = "okay";
> +};
> +
> +&adc2 {
> + vref-supply = <®_vref_1v8>;
> + status = "okay";
> +};
> +
> +&cpu0 {
> + cpu-supply = <&sw1a_reg>;
> +};
> +
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet1>;
> + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
> + <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
> + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
> + assigned-clock-rates = <0>, <100000000>;
> + phy-mode = "rgmii";
> + phy-handle = <ðphy0>;
> + fsl,magic-packet;
> + phy-reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +
> + /*
> + * The skew settings should be in the ethernet-phy subnode, but
> + * currently this doesn't work.
> + *
> + * All skews are offset since hardware skew values for the ksz9031
> + * range from a negative skew to a positive skew. The increment
> + * step is 60ps.
> + * See the micrel-ksz90x1.txt Documentation file for details.
> + */
> +
> + /* -900ps up t0 +960ps
> + * 0 (reg val 0) -> -900 ps
> + * 900 (reg val 15) -> 0 ps
> + * 1860 (reg val 31) -> +960 ps
> + *
> + */
> + rxc-skew-ps = <1860>; /* */
> + txc-skew-ps = <1860>; /* */
> +
> + /* -420ps up to 480ps
> + * 0 (reg val 0) -> -420 ps
> + * 420 (reg val 7) -> 0 ps
> + * 900 (reg val 15) -> +480 ps
> + * */
> + txd0-skew-ps = <420>; /* 0 ps */
> + txd1-skew-ps = <420>; /* 0 ps */
> + txd2-skew-ps = <420>; /* 0 ps */
> + txd3-skew-ps = <420>; /* 0 ps */
> + rxd0-skew-ps = <420>; /* 0 ps */
> + rxd1-skew-ps = <420>; /* 0 ps */
> + rxd2-skew-ps = <420>; /* 0 ps */
> + rxd3-skew-ps = <420>; /* 0 ps */
> + txen-skew-ps = <420>; /* 0 ps */
> + rxdv-skew-ps = <420>; /* 0 ps */
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy at 0 {
> + reg = <1>;
> + };
> +
> + ethphy1: ethernet-phy at 1 {
> + reg = <2>;
> + };
> + };
> +};
> +
> +&fec2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet2>;
> + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
> + <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
> + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
> + assigned-clock-rates = <0>, <100000000>;
> + phy-mode = "rgmii";
> + phy-handle = <ðphy1>;
> + fsl,magic-packet;
> + status = "disabled";
> +};
> +
> +&flexcan2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2>;
> + xceiver-supply = <®_can2_3v3>;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +
> + i2c_eeprom: i2c_eeprom at 50 {
> + compatible = "microchip,24lc512";
> + reg = <0x50>;
> + };
> +
> + pmic: pfuze3000 at 8 {
> + compatible = "fsl,pfuze3000";
> + reg = <0x08>;
> +
> + regulators {
> + sw1a_reg: sw1a {
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1475000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + /* use sw1c_reg to align with pfuze100/pfuze200 */
> + sw1c_reg: sw1b {
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1475000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + sw2_reg: sw2 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw3a_reg: sw3 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1650000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + swbst_reg: swbst {
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5150000>;
> + };
> +
> + snvs_reg: vsnvs {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vref_reg: vrefddr {
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vgen1_reg: vldo1 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vgen2_reg: vldo2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + };
> +
> + vgen3_reg: vccsd {
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vgen4_reg: v33 {
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vgen5_reg: vldo3 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vgen6_reg: vldo4 {
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-always-on;
> + };
> + };
> + };
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +};
> +
> +&i2c3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + status = "okay";
> +};
> +
> +&i2c4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c4>;
> + status = "okay";
> +
> + codec: wm8960 at 1a {
> + compatible = "wlf,wm8960";
> + reg = <0x1a>;
> + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
> + clock-names = "mclk";
> + wlf,shared-lrclk;
> + };
> +};
> +
> +&snvs_pwrkey {
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
> + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
> + status = "okay";
> +};
> +
> +&uart6 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart6>;
> + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
> + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
> + uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&usbotg1 {
> + vbus-supply = <®_usb_otg1_vbus>;
> + status = "okay";
> +};
> +
> +&usbotg2 {
> + vbus-supply = <®_usb_otg2_vbus>;
> + dr_mode = "host";
> + status = "okay";
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + cd-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
> + wp-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
> + vmmc-supply = <®_sd1_vmmc>;
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step= <2>;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc2>;
> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
> + wakeup-source;
> + keep-power-in-suspend;
> + non-removable;
> + vmmc-supply = <®_sd2_vmmc>;
> + fsl,tuning-step = <2>;
> + status = "okay";
> +};
> +
> +&usdhc3 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc3>;
> + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
> + assigned-clock-rates = <400000000>;
> + bus-width = <8>;
> + fsl,tuning-step = <2>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + fsl,ext-reset-output;
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hog>;
> +
> + imx7d-sdb {
> + pinctrl_sd2_vmmc_reg: pinctrl_sd2_vmmc_reg {
> + fsl,pins = <
> + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 /* WL_REG_ON */
> + >;
> + };
> +
> + pinctrl_enet1: enet1grp {
> + fsl,pins = <
> + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
> + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
> + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
> + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
> + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
> + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
> + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
> + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
> + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
> + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
> + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
> + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
> + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
> + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
> + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* ETH_RESET */
> + >;
> + };
> +
> + pinctrl_enet2: enet2grp {
> + fsl,pins = <
> + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
> + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
> + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
> + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
> + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
> + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
> + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
> + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
> + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
> + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
> + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
> + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
> + >;
> + };
> +
> + pinctrl_flexcan2: flexcan2grp {
> + fsl,pins = <
> + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
> + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
> + >;
> + };
> +
> + pinctrl_flexcan2_reg: flexcan2reggrp {
> + fsl,pins = <
> + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */
> + >;
> + };
> +
> + pinctrl_gpio_keys: gpio_keysgrp {
> + fsl,pins = <
> + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59
> + MX7D_PAD_SD2_WP__GPIO5_IO10 0x59
> + >;
> + };
> +
> + pinctrl_hog: hoggrp {
> + fsl,pins = <
> + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
> + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
> + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
> + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
> + >;
> + };
> +
> + pinctrl_i2c4: i2c4grp {
> + fsl,pins = <
> + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
> + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
> + >;
> + };
> +
> + pinctrl_spi4: spi4grp {
> + fsl,pins = <
> + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
> + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
> + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
> + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
> + >;
> + };
> +
> + pinctrl_uart6: uart6grp {
> + fsl,pins = <
> + MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
> + MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
> + MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
> + MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX7D_PAD_SD1_CMD__SD1_CMD 0x59
> + MX7D_PAD_SD1_CLK__SD1_CLK 0x19
> + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
> + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
> + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
> + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
> + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
> + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
> + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
> + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX7D_PAD_SD2_CMD__SD2_CMD 0x59
> + MX7D_PAD_SD2_CLK__SD2_CLK 0x19
> + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
> + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
> + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
> + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
> + >;
> + };
> +
> + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
> + fsl,pins = <
> + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
> + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
> + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
> + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
> + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
> + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
> + >;
> + };
> +
> + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
> + fsl,pins = <
> + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
> + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
> + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
> + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
> + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
> + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
> + >;
> + };
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> + MX7D_PAD_SD3_CMD__SD3_CMD 0x59
> + MX7D_PAD_SD3_CLK__SD3_CLK 0x19
> + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
> + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
> + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
> + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
> + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
> + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
> + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
> + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
> + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
> + >;
> + };
> +
> + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
> + fsl,pins = <
> + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
> + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
> + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
> + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
> + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
> + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
> + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
> + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
> + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
> + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
> + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
> + >;
> + };
> +
> + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
> + fsl,pins = <
> + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
> + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
> + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
> + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
> + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
> + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
> + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
> + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
> + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
> + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
> + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
> + >;
> + };
> + };
> +};
> +
> +&pwm1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm1>;
> + status = "okay";
> +};
> +
> +&iomuxc_lpsr {
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
> + >;
> + };
> +
> + pinctrl_pwm1: pwm1grp {
> + fsl,pins = <
> + MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30
> + >;
> + };
> +
> + pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp {
> + fsl,pins = <
> + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
> + >;
> + };
> +};
> +
> +/* disable epdc, conflict with qspi */
> +&epdc {
> + status = "disabled";
> +};
> +
> +&iomuxc {
> + qspi1 {
> + pinctrl_qspi1_1: qspi1grp_1 {
> + fsl,pins = <
> + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51
> + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51
> + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51
> + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51
> + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51
> + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51
> + >;
> + };
> + };
> +};
> +
> +&qspi1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_qspi1_1>;
> + status = "okay";
> + ddrsmp=<0>;
> +
> + flash0: mx25l51245g at 0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "macronix,mx25l25645g";
> + spi-max-frequency = <29000000>;
> + /* take off one dummy cycle */
> + spi-nor,ddr-quad-read-dummy = <5>;
> + reg = <0>;
> + };
> +};
> diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
> index c8146c3509..64c15cbc07 100644
> --- a/arch/arm/mach-imx/mx7/Kconfig
> +++ b/arch/arm/mach-imx/mx7/Kconfig
> @@ -76,6 +76,14 @@ config TARGET_COLIBRI_IMX7
> select DM_THERMAL
> imply CMD_DM
>
> +config TARGET_IMX7_CM
> + bool "imx7-cm"
> + select BOARD_LATE_INIT
> + select DM
> + select DM_THERMAL
> + select MX7D
> + imply CMD_DM
> +
> endchoice
>
> config SYS_SOC
> @@ -87,5 +95,5 @@ source "board/novtech/meerkat96/Kconfig"
> source "board/technexion/pico-imx7d/Kconfig"
> source "board/toradex/colibri_imx7/Kconfig"
> source "board/warp7/Kconfig"
> -
> +source "board/ronetix/imx7-cm/Kconfig"
> endif
> diff --git a/board/ronetix/imx7-cm/Kconfig b/board/ronetix/imx7-cm/Kconfig
> new file mode 100644
> index 0000000000..ef7565419f
> --- /dev/null
> +++ b/board/ronetix/imx7-cm/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_IMX7_CM
> +
> +config SYS_BOARD
> + default "imx7-cm"
> +
> +config SYS_VENDOR
> + default "ronetix"
> +
> +config SYS_CONFIG_NAME
> + default "imx7-cm"
> +
> +endif
> diff --git a/board/ronetix/imx7-cm/MAINTAINERS b/board/ronetix/imx7-cm/MAINTAINERS
> new file mode 100644
> index 0000000000..5faa2c5c8b
> --- /dev/null
> +++ b/board/ronetix/imx7-cm/MAINTAINERS
> @@ -0,0 +1,6 @@
> +IMX7-CM BOARD
> +M: Ilko Iliev <iliev at ronetix.at>
> +S: Maintained
> +F: board/ronetix/imx7-cm/
> +F: include/configs/imx7-cm.h
> +F: configs/imx7-cm_defconfig
> diff --git a/board/ronetix/imx7-cm/Makefile b/board/ronetix/imx7-cm/Makefile
> new file mode 100644
> index 0000000000..34021b00fd
> --- /dev/null
> +++ b/board/ronetix/imx7-cm/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +# (C) Copyright 2015 Freescale Semiconductor, Inc.
> +
> +obj-y := imx7-cm.o
> diff --git a/board/ronetix/imx7-cm/imx7-cm.c b/board/ronetix/imx7-cm/imx7-cm.c
> new file mode 100644
> index 0000000000..b8888f4eae
> --- /dev/null
> +++ b/board/ronetix/imx7-cm/imx7-cm.c
> @@ -0,0 +1,210 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
> + */
> +
> +#include <init.h>
> +#include <net.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/mx7-pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/gpio.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <asm/io.h>
> +#include <linux/delay.h>
> +#include <linux/sizes.h>
> +#include <common.h>
> +#include <fsl_esdhc_imx.h>
> +#include <mmc.h>
> +#include <miiphy.h>
> +#include <power/pmic.h>
> +#include <power/pfuze3000_pmic.h>
> +#include "../../freescale/common/pfuze.h"
> +#include <i2c.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +#include <asm/arch/crm_regs.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* status LED */
> +#define GPIO_LED_STATUS IMX_GPIO_NR(2, 7)
> +
> +/* reset PHY */
> +#define GPIO_PHY_RESET IMX_GPIO_NR(2, 4)
> +
> +/* LCD back light enable: 1- ON, 0 - OFF */
> +#define GPIO_LCD_BL_EN IMX_GPIO_NR(1, 13)
> +
> +/* LCD back light PWM */
> +#define GPIO_LCD_BL_PWM IMX_GPIO_NR(1, 1)
> +
> +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
> + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
> +
> +int dram_init(void)
> +{
> + gd->ram_size = PHYS_SDRAM_SIZE;
> +
> + return 0;
> +}
> +
> +static iomux_v3_cfg_t const wdog_pads[] = {
> + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const uart1_pads[] = {
> + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static void setup_iomux_uart(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
> +}
> +
> +int board_mmc_get_env_dev(int devno)
> +{
> + if (devno == 2)
> + devno--;
> +
> + return devno;
> +}
> +
> +int mmc_map_to_kernel_blk(int dev_no)
> +{
> + if (dev_no == 1)
> + dev_no++;
> +
> + return dev_no;
> +}
> +
> +#ifdef CONFIG_FEC_MXC
> +static int setup_fec(void)
> +{
> + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
> + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
> +
> + int ret;
> + unsigned int gpio = GPIO_PHY_RESET;
> +
> + ret = gpio_request(gpio, "fec_rst");
> + if (ret && ret != -EBUSY) {
> + printf("gpio: requesting pin %u failed\n", gpio);
> + return ret;
> + }
> +
> + gpio_direction_output(gpio, 0);
> + udelay(500);
> + gpio_direction_output(gpio, 1);
> + udelay(10000);
> +
> + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
> + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
> + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
> + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
> +
> + /* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/
> + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
> + (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |
> + IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);
> +
> + return set_clk_enet(ENET_125MHZ);
> +}
> +#endif
> +
> +#ifdef CONFIG_FSL_QSPI
> +int board_qspi_init(void)
> +{
> + /* Set the clock */
> + set_clk_qspi();
> +
> + return 0;
> +}
> +#endif
> +
> +int board_early_init_f(void)
> +{
> + setup_iomux_uart();
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +
> + /* turn ON the status LED */
> + gpio_request(GPIO_LED_STATUS, "LED status");
> + gpio_direction_output(GPIO_LED_STATUS, 0);
> +
> +#ifdef CONFIG_FEC_MXC
> + setup_fec();
> +#endif
> +
> +#ifdef CONFIG_FSL_QSPI
> + board_qspi_init();
> +#endif
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_DM_PMIC
> +int power_init_board(void)
> +{
> + struct udevice *dev;
> + int ret, dev_id, rev_id;
> +
> + ret = pmic_get("pfuze3000 at 8", &dev);
> + if (ret == -ENODEV)
> + return 0;
> + if (ret != 0)
> + return ret;
> +
> + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
> + rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
> + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
> +
> + pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
> +
> + /*
> + * Set the voltage of VLDO4 output to 2.8V which feeds
> + * the MIPI DSI and MIPI CSI inputs.
> + */
> + pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA);
> +
> + return 0;
> +}
> +#endif
> +
> +int board_late_init(void)
> +{
> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> +
> + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
> +
> + set_wdog_reset(wdog);
> +
> + /*
> + * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
> + * since we use PMIC_PWRON to reset the board.
> + */
> + clrsetbits_le16(&wdog->wcr, 0, 0x10);
> +
> + return 0;
> +}
> +
> +int checkboard(void)
> +{
> + char *mode;
> +
> + if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
> + mode = "secure";
> + else
> + mode = "non-secure";
> +
> + printf("Board: i.MX7-CM in %s mode\n", mode);
> +
> + return 0;
> +}
> diff --git a/board/ronetix/imx7-cm/imximage.cfg b/board/ronetix/imx7-cm/imximage.cfg
> new file mode 100644
> index 0000000000..af46ebc671
> --- /dev/null
> +++ b/board/ronetix/imx7-cm/imximage.cfg
> @@ -0,0 +1,104 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
> + *
> + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +
> +#define __ASSEMBLY__
> +#include <config.h>
> +
> +/* image version */
> +
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : sd
> + */
> +
> +BOOT_FROM sd
> +
> +/*
> + * Secure boot support
> + */
> +#ifdef CONFIG_IMX_HAB
> +CSF CONFIG_CSF_SIZE
> +#endif
> +
> +/*
> + * Device Configuration Data (DCD)
> + *
> + * Each entry must have the format:
> + * Addr-type Address Value
> + *
> + * where:
> + * Addr-type register length (1,2 or 4 bytes)
> + * Address absolute address of the register
> + * value value to be stored in the register
> + */
> +
> +DATA 4 0x30340004 0x4F400005
> +/* Clear then set bit30 to ensure exit from DDR retention */
> +DATA 4 0x30360388 0x40000000
> +DATA 4 0x30360384 0x40000000
> +
> +DATA 4 0x30391000 0x00000002
> +DATA 4 0x307a0000 0x01040001
> +DATA 4 0x307a01a0 0x80400003
> +DATA 4 0x307a01a4 0x00100020
> +DATA 4 0x307a01a8 0x80100004
> +DATA 4 0x307a0064 0x00400046
> +DATA 4 0x307a0490 0x00000001
> +DATA 4 0x307a00d0 0x00020083
> +DATA 4 0x307a00d4 0x00690000
> +DATA 4 0x307a00dc 0x09300004
> +DATA 4 0x307a00e0 0x04080000
> +DATA 4 0x307a00e4 0x00100004
> +DATA 4 0x307a00f4 0x0000033f
> +DATA 4 0x307a0100 0x09081109
> +DATA 4 0x307a0104 0x0007020d
> +DATA 4 0x307a0108 0x03040407
> +DATA 4 0x307a010c 0x00002006
> +DATA 4 0x307a0110 0x04020205
> +DATA 4 0x307a0114 0x03030202
> +DATA 4 0x307a0120 0x00000803
> +DATA 4 0x307a0180 0x00800020
> +DATA 4 0x307a0184 0x02000100
> +DATA 4 0x307a0190 0x02098204
> +DATA 4 0x307a0194 0x00030303
> +DATA 4 0x307a0200 0x00000016
> +DATA 4 0x307a0204 0x00080808
> +DATA 4 0x307a0210 0x00000f0f
> +DATA 4 0x307a0214 0x07070707
> +DATA 4 0x307a0218 0x0f070707
> +DATA 4 0x307a0240 0x06000604
> +DATA 4 0x307a0244 0x00000001
> +DATA 4 0x30391000 0x00000000
> +DATA 4 0x30790000 0x17420f40
> +DATA 4 0x30790004 0x10210100
> +DATA 4 0x30790010 0x00060807
> +DATA 4 0x307900b0 0x1010007e
> +DATA 4 0x3079009c 0x00000b24
> +DATA 4 0x30790020 0x0A0A0A0A
> +DATA 4 0x30790030 0x06060606
> +DATA 4 0x30790050 0x01000010
> +DATA 4 0x30790050 0x00000010
> +
> +DATA 4 0x307900c0 0x0e407304
> +DATA 4 0x307900c0 0x0e447304
> +DATA 4 0x307900c0 0x0e447306
> +
> +CHECK_BITS_SET 4 0x307900c4 0x1
> +
> +DATA 4 0x307900c0 0x0e447304
> +DATA 4 0x307900c0 0x0e407304
> +
> +DATA 4 0x30384130 0x00000000
> +DATA 4 0x30340020 0x00000178
> +DATA 4 0x30384130 0x00000002
> +DATA 4 0x30790018 0x0000000f
> +
> +CHECK_BITS_SET 4 0x307a0004 0x1
> diff --git a/configs/imx7_cm_defconfig b/configs/imx7_cm_defconfig
> new file mode 100644
> index 0000000000..92d7c10da5
> --- /dev/null
> +++ b/configs/imx7_cm_defconfig
> @@ -0,0 +1,97 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_MX7=y
> +CONFIG_ENV_SIZE=0x2000
> +CONFIG_ENV_OFFSET=0xC0000
> +CONFIG_DM_GPIO=y
> +CONFIG_TARGET_IMX7_CM=y
> +CONFIG_NR_DRAM_BANKS=1
> +# CONFIG_ARMV7_VIRT is not set
> +CONFIG_IMX_RDC=y
> +CONFIG_IMX_BOOTAUX=y
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ronetix/imx7-cm/imximage.cfg"
> +CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
> +# CONFIG_CONSOLE_MUX is not set
> +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> +CONFIG_BOUNCE_BUFFER=y
> +# CONFIG_CMD_BOOTD is not set
> +# CONFIG_BOOTM_NETBSD is not set
> +# CONFIG_BOOTM_PLAN9 is not set
> +# CONFIG_BOOTM_RTEMS is not set
> +# CONFIG_CMD_IMI is not set
> +# CONFIG_CMD_XIMG is not set
> +# CONFIG_CMD_EXPORTENV is not set
> +# CONFIG_CMD_IMPORTENV is not set
> +CONFIG_CMD_MEMTEST=y
> +CONFIG_SYS_MEMTEST_START=0x80000000
> +CONFIG_SYS_MEMTEST_END=0xa0000000
> +CONFIG_CMD_DFU=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_EEPROM=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_BMP=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_PMIC=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_CMD_EXT4_WRITE=y
> +# CONFIG_ISO_PARTITION is not set
> +# CONFIG_EFI_PARTITION is not set
> +CONFIG_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="imx7-cm"
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_DFU_MMC=y
> +CONFIG_DFU_RAM=y
> +CONFIG_DM_I2C=y
> +CONFIG_DM_MMC=y
> +CONFIG_SUPPORT_EMMC_BOOT=y
> +CONFIG_MMC_IO_VOLTAGE=y
> +CONFIG_MMC_UHS_SUPPORT=y
> +CONFIG_MMC_HS200_SUPPORT=y
> +CONFIG_FSL_USDHC=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SF_DEFAULT_MODE=0
> +CONFIG_SF_DEFAULT_SPEED=40000000
> +CONFIG_PHYLIB=y
> +CONFIG_PHY_MICREL=y
> +CONFIG_PHY_MICREL_KSZ90X1=y
> +CONFIG_DM_ETH=y
> +CONFIG_DM_MDIO=y
> +CONFIG_DM_MDIO_MUX=y
> +CONFIG_FEC_MXC=y
> +CONFIG_RGMII=y
> +CONFIG_MII=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_IMX7=y
> +CONFIG_DM_PMIC=y
> +CONFIG_DM_PMIC_PFUZE100=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_PFUZE100=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_SPI=y
> +CONFIG_DM_SPI=y
> +CONFIG_FSL_QSPI=y
> +CONFIG_USB=y
> +CONFIG_DM_USB=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_MXC_USB_OTG_HACTIVE=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_MANUFACTURER="FSL"
> +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> +CONFIG_CI_UDC=y
> +CONFIG_USB_GADGET_DOWNLOAD=y
> +CONFIG_USB_HOST_ETHER=y
> +CONFIG_USB_ETHER_ASIX=y
> +CONFIG_VIDEO=y
> +CONFIG_DM_VIDEO=y
> +CONFIG_ERRNO_STR=y
> diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h
> new file mode 100644
> index 0000000000..07850fe65c
> --- /dev/null
> +++ b/include/configs/imx7-cm.h
> @@ -0,0 +1,157 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
> + *
> + * Configuration settings for the Freescale i.MX7D SABRESD board.
> + */
> +
> +#ifndef __MX7D_SABRESD_CONFIG_H
> +#define __MX7D_SABRESD_CONFIG_H
> +
> +#include "mx7_common.h"
> +
> +#define PHYS_SDRAM_SIZE SZ_512M
> +
> +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
> +
> +/* MMC Config*/
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +
> +/* I2C configs */
> +#define CONFIG_SYS_I2C_MXC
> +#define CONFIG_SYS_I2C_SPEED 100000
> +
> +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
> +
> +#ifdef CONFIG_IMX_BOOTAUX
> +/* Set to QSPI1 A flash at default */
> +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000
> +
> +#define UPDATE_M4_ENV \
> + "m4image=m4_qspi.bin\0" \
> + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
> + "update_m4_from_sd=" \
> + "if sf probe 0:0; then " \
> + "if run loadm4image; then " \
> + "setexpr fw_sz ${filesize} + 0xffff; " \
> + "setexpr fw_sz ${fw_sz} / 0x10000; " \
> + "setexpr fw_sz ${fw_sz} * 0x10000; " \
> + "sf erase 0x0 ${fw_sz}; " \
> + "sf write ${loadaddr} 0x0 ${filesize}; " \
> + "fi; " \
> + "fi\0" \
> + "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
> +#else
> +#define UPDATE_M4_ENV ""
> +#endif
> +
> +#define CONFIG_MFG_ENV_SETTINGS \
> + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
> + "rdinit=/linuxrc " \
> + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
> + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
> + "g_mass_storage.iSerialNumber=\"\" "\
> + "clk_ignore_unused "\
> + "\0" \
> + "initrd_addr=0x83800000\0" \
> + "initrd_high=0xffffffff\0" \
> + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
> +
> +#define CONFIG_DFU_ENV_SETTINGS \
> + "dfu_alt_info=image raw 0 0x800000;"\
> + "u-boot raw 0 0x4000;"\
> + "bootimg part 0 1;"\
> + "rootfs part 0 2\0" \
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + UPDATE_M4_ENV \
> + CONFIG_MFG_ENV_SETTINGS \
> + CONFIG_DFU_ENV_SETTINGS \
> + "script=boot.scr\0" \
> + "image=zImage\0" \
> + "console=ttymxc0\0" \
> + "fdt_high=0xffffffff\0" \
> + "finduuid=part uuid mmc 0:1 uuid\0" \
> + "initrd_high=0xffffffff\0" \
> + "fdtfile=imx7-cm.dtb\0" \
> + "fdt_addr=0x83000000\0" \
> + "fdt_addr_r=0x83000000\0" \
> + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
> + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
> + "ramdisk_addr_r=0x83100000\0" \
> + "ramdiskaddr=0x83100000\0" \
> + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
> + "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
> + BOOTENV
> +
> +#define BOOT_TARGET_DEVICES(func) \
> + func(MMC, mmc, 0) \
> + func(DHCP, dhcp, na) \
> + func(PXE, pxe, na)
> +
> +#include <config_distro_bootcmd.h>
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +#define CONFIG_SYS_HZ 1000
> +
> +/* Physical Memory Map */
> +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
> +
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
> +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* environment organization */
> +
> +/*
> + * If want to use nand, define CONFIG_NAND_MXS and rework board
> + * to support nand, since emmc has pin conflicts with nand
> + */
> +#ifdef CONFIG_NAND_MXS
> +/* NAND stuff */
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define CONFIG_SYS_NAND_BASE 0x40000000
> +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> +#define CONFIG_SYS_NAND_ONFI_DETECTION
> +
> +/* DMA stuff, needed for GPMI/MXS NAND support */
> +#endif
> +
> +#ifdef CONFIG_NAND_MXS
> +#define CONFIG_SYS_FSL_USDHC_NUM 1
> +#else
> +#define CONFIG_SYS_FSL_USDHC_NUM 2
> +#endif
> +
> +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
> +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
> +
> +/* USB Configs */
> +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
> +
> +#define CONFIG_IMX_THERMAL
> +
> +#define CONFIG_USBD_HS
> +
> +#ifdef CONFIG_VIDEO
> +#define CONFIG_VIDEO_MXS
> +#define CONFIG_VIDEO_LOGO
> +#define CONFIG_SPLASH_SCREEN
> +#define CONFIG_SPLASH_SCREEN_ALIGN
> +#define CONFIG_BMP_16BPP
> +#define CONFIG_VIDEO_BMP_RLE8
> +#define CONFIG_VIDEO_BMP_LOGO
> +#endif
> +
> +#endif /* __CONFIG_H */
>
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
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