[PATCH v5 5/7] riscv: dts: Add device tree for Microchip Icicle Kit
Padmarao Begari
padmarao.b at gmail.com
Fri Dec 11 07:16:02 CET 2020
Hi Bin,
On Thu, Dec 10, 2020 at 6:48 PM Bin Meng <bmeng.cn at gmail.com> wrote:
> Hi Padmarao,
>
> On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> <padmarao.begari at microchip.com> wrote:
> >
> > Add device tree for Microchip PolarFire SoC Icicle Kit.
> >
> > Signed-off-by: Padmarao Begari <padmarao.begari at microchip.com>
> > Reviewed-by: Anup Patel <anup.patel at wdc.com>
> > ---
> > arch/riscv/dts/Makefile | 1 +
> > .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
> > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 ++++++++++++++++++
> > 3 files changed, 436 insertions(+)
> > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> >
> > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> > index 3a6f96c67d..01331b0aa1 100644
> > --- a/arch/riscv/dts/Makefile
> > +++ b/arch/riscv/dts/Makefile
> > @@ -3,6 +3,7 @@
> > dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
> > dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
> > dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> > +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
> >
> > targets += $(dtb-y)
> >
> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> > new file mode 100644
> > index 0000000000..f60283fb6b
> > --- /dev/null
> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> > @@ -0,0 +1,14 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2020 Microchip Technology Inc.
> > + * Padmarao Begari <padmarao.begari at microchip.com>
> > + */
> > +
> > +/ {
> > + aliases {
> > + cpu1 = &cpu1;
> > + cpu2 = &cpu2;
> > + cpu3 = &cpu3;
> > + cpu4 = &cpu4;
> > + };
> > +};
> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > new file mode 100644
> > index 0000000000..f5478bf201
> > --- /dev/null
> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > @@ -0,0 +1,421 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +#include "dt-bindings/clock/microchip,mpfs-clock.h"
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ 1000000
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "Microchip MPFS Icicle Kit";
> > + compatible = "microchip,mpfs-icicle-kit";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + ethernet0 = &emac1;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0";
> > + };
> > +
> > + cpucomplex: cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <RTCCLK_FREQ>;
> > + cpu0: cpu at 0 {
> > + clocks = <&clkcfg CLK_CPU>;
> > + compatible = "sifive,e51", "sifive,rocket0",
> "riscv";
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <128>;
> > + i-cache-size = <16384>;
> > + reg = <0>;
> > + riscv,isa = "rv64imac";
> > + status = "disabled";
> > + operating-points = <
> > + /* kHz uV */
> > + 600000 1100000
> > + 300000 950000
> > + 150000 750000
> > + >;
> > + cpu0intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + cpu1: cpu at 1 {
> > + clocks = <&clkcfg CLK_CPU>;
> > + compatible = "sifive,u54-mc", "sifive,rocket0",
> "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <1>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > + operating-points = <
> > + /* kHz uV */
> > + 600000 1100000
> > + 300000 950000
> > + 150000 750000
> > + >;
> > + cpu1intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + cpu2: cpu at 2 {
> > + clocks = <&clkcfg CLK_CPU>;
> > + compatible = "sifive,u54-mc", "sifive,rocket0",
> "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <2>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > + operating-points = <
> > + /* kHz uV */
> > + 600000 1100000
> > + 300000 950000
> > + 150000 750000
> > + >;
> > + cpu2intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + cpu3: cpu at 3 {
> > + clocks = <&clkcfg CLK_CPU>;
> > + compatible = "sifive,u54-mc", "sifive,rocket0",
> "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <3>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > + operating-points = <
> > + /* kHz uV */
> > + 600000 1100000
> > + 300000 950000
> > + 150000 750000
> > + >;
> > + cpu3intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + cpu4: cpu at 4 {
> > + clocks = <&clkcfg CLK_CPU>;
> > + compatible = "sifive,u54-mc", "sifive,rocket0",
> "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <4>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > + operating-points = <
> > + /* kHz uV */
> > + 600000 1100000
> > + 300000 950000
> > + 150000 750000
> > + >;
> > + cpu4intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + };
> > + ddr: memory at 80000000 {
> > + device_type = "memory";
> > + reg = <0x0 0x80000000 0x0 0x40000000>;
> > + clocks = <&clkcfg CLK_DDRC>;
> > + };
> > + soc: soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + compatible = "microchip,mpfs-icicle-kit", "simple-bus";
> > + ranges;
> > + clint0: clint at 2000000 {
> > + compatible = "riscv,clint0";
> > + interrupts-extended = <&cpu0intc 3 &cpu0intc 7
> > + &cpu1intc 3 &cpu1intc 7
> > + &cpu2intc 3 &cpu2intc 7
> > + &cpu3intc 3 &cpu3intc 7
> > + &cpu4intc 3 &cpu4intc 7>;
> > + reg = <0x0 0x2000000 0x0 0x10000>;
> > + reg-names = "control";
> > + clock-frequency = <RTCCLK_FREQ>;
> > + };
> > + cachecontroller: cache-controller at 2010000 {
> > + compatible = "sifive,fu540-c000-ccache", "cache";
> > + cache-block-size = <64>;
> > + cache-level = <2>;
> > + cache-sets = <1024>;
> > + cache-size = <2097152>;
> > + cache-unified;
> > + interrupt-parent = <&plic>;
> > + interrupts = <1 2 3>;
> > + reg = <0x0 0x2010000 0x0 0x1000>;
> > + };
> > + plic: interrupt-controller at c000000 {
> > + #interrupt-cells = <1>;
> > + compatible = "sifive,plic-1.0.0";
> > + reg = <0x0 0xc000000 0x0 0x4000000>;
> > + riscv,max-priority = <7>;
> > + riscv,ndev = <186>;
> > + interrupt-controller;
> > + interrupts-extended = <
> > + &cpu0intc 11
> > + &cpu1intc 11 &cpu1intc 9
> > + &cpu2intc 11 &cpu2intc 9
> > + &cpu3intc 11 &cpu3intc 9
> > + &cpu4intc 11 &cpu4intc 9>;
> > + };
> > + uart0: serial at 20000000 {
> > + compatible = "ns16550a";
> > + reg = <0x0 0x20000000 0x0 0x400>;
> > + reg-io-width = <4>;
> > + reg-shift = <2>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <90>;
> > + clock-frequency = <150000000>;
> > + clocks = <&clkcfg CLK_MMUART0>;
> > + status = "okay";
> > + };
> > + refclk: refclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <600000000>;
> > + clock-output-names = "msspllclk";
> > + };
> > + clkcfg: clkcfg at 20002000 {
> > + compatible = "microchip,mpfs-clkcfg";
> > + reg = <0x0 0x20002000 0x0 0x1000>;
> > + reg-names = "mss_sysreg";
> > + clocks = <&refclk>;
> > + #clock-cells = <1>;
> > + clock-output-names = "cpu", "axi", "ahb", "envm",
> > + "mac0", "mac1", "mmc", "timer",
> > + "mmuart0", "mmuart1", "mmuart2",
> > + "mmuart3", "mmuart4", "spi0",
> "spi1",
> > + "i2c0", "i2c1", "can0", "can1",
> "usb",
> > + "reserved", "rtc", "qspi",
> "gpio0",
> > + "gpio1", "gpio2", "ddrc", "fic0",
> > + "fic1", "fic2", "fic3", "athena",
> > + "cfm";
> > + };
> > + emmc: mmc at 20008000 {
> > + compatible = "cdns,sd4hc";
> > + reg = <0x0 0x20008000 0x0 0x1000>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <88 89>;
> > + pinctrl-names = "default";
> > + clocks = <&clkcfg CLK_MMC>;
> > + bus-width = <4>;
> > + cap-mmc-highspeed;
> > + mmc-ddr-3_3v;
> > + max-frequency = <200000000>;
> > + non-removable;
> > + no-sd;
> > + no-sdio;
> > + voltage-ranges = <3300 3300>;
> > + status = "okay";
> > + };
> > + sdcard: sd at 20008000 {
> > + compatible = "cdns,sd4hc";
> > + reg = <0x0 0x20008000 0x0 0x1000>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <88>;
> > + pinctrl-names = "default";
> > + clocks = <&clkcfg CLK_MMC>;
> > + bus-width = <4>;
> > + disable-wp;
> > + cap-sd-highspeed;
> > + card-detect-delay = <200>;
> > + sd-uhs-sdr12;
> > + sd-uhs-sdr25;
> > + sd-uhs-sdr50;
> > + sd-uhs-sdr104;
> > + max-frequency = <200000000>;
> > + status = "disabled";
> > + };
> > + uart1: serial at 20100000 {
> > + compatible = "ns16550a";
> > + reg = <0x0 0x20100000 0x0 0x400>;
> > + reg-io-width = <4>;
> > + reg-shift = <2>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <91>;
> > + clock-frequency = <150000000>;
> > + clocks = <&clkcfg CLK_MMUART1>;
> > + status = "okay";
> > + };
> > + uart2: serial at 20102000 {
> > + compatible = "ns16550a";
> > + reg = <0x0 0x20102000 0x0 0x400>;
> > + reg-io-width = <4>;
> > + reg-shift = <2>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <92>;
> > + clock-frequency = <150000000>;
> > + clocks = <&clkcfg CLK_MMUART2>;
> > + status = "okay";
> > + };
> > + uart3: serial at 20104000 {
> > + compatible = "ns16550a";
> > + reg = <0x0 0x20104000 0x0 0x400>;
> > + reg-io-width = <4>;
> > + reg-shift = <2>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <93>;
> > + clock-frequency = <150000000>;
> > + clocks = <&clkcfg CLK_MMUART3>;
> > + status = "okay";
> > + };
> > + i2c0: i2c at 02010a000 {
>
> i2c at 2010a000 (as newer version dtc complains about it)
>
>
Ok
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "microchip,mpfs-mss-i2c";
> > + reg = <0x0 0x2010a000 0x0 0x1000>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <58>;
> > + clocks = <&clkcfg CLK_I2C0>;
> > + status = "disabled";
> > + };
> > + i2c1: i2c at 02010b000 {
>
> i2c at 2010b000
>
>
Ok
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "microchip,mpfs-mss-i2c";
> > + reg = <0x0 0x2010b000 0x0 0x1000>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <61>;
> > + clocks = <&clkcfg CLK_I2C1>;
> > + status = "disabled";
> > + pac193x at 0x10 {
>
> pac193x at 10
>
>
Ok
> > + compatible = "microchip,pac1934";
> > + reg = <0x10>;
> > + samp-rate = <64>;
> > + status = "disabled";
> > + ch1: channel at 0 {
> > + uohms-shunt-res = <10000>;
> > + rail-name = "VDD";
> > + channel_enabled;
> > + };
> > + ch2: channel at 1 {
> > + uohms-shunt-res = <10000>;
> > + rail-name = "VDDA25";
> > + channel_enabled;
> > + };
> > + ch3: channel at 2 {
> > + uohms-shunt-res = <10000>;
> > + rail-name = "VDD25";
> > + channel_enabled;
> > + };
> > + ch4: channel at 3 {
> > + uohms-shunt-res = <10000>;
> > + rail-name = "VDDA";
> > + channel_enabled;
> > + };
> > + };
> > + };
> > + emac0: ethernet at 20110000 {
> > + compatible = "microchip,mpfs-mss-gem";
> > + reg = <0x0 0x20110000 0x0 0x2000>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <64 65 66 67>;
> > + local-mac-address = [56 34 00 FC 00 02];
> > + phy-mode = "sgmii";
> > + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AXI>;
> > + clock-names = "pclk", "hclk";
> > + status = "disabled";
> > +
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + phy-handle = <&phy0>;
> > + phy0: ethernet-phy at 8 {
> > + reg = <8>;
> > + ti,fifo-depth = <0x01>;
> > + };
> > + };
> > + emac1: ethernet at 20112000 {
> > + compatible = "microchip,mpfs-mss-gem";
> > + reg = <0x0 0x20112000 0x0 0x2000>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <70 71 72 73>;
> > + local-mac-address = [00 00 00 00 00 00];
> > + phy-mode = "sgmii";
> > + clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
> > + clock-names = "pclk", "hclk";
> > + status = "okay";
> > +
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + phy-handle = <&phy1>;
> > + phy1: ethernet-phy at 9 {
> > + reg = <9>;
> > + ti,fifo-depth = <0x01>;
> > + };
> > + };
> > + gpio: gpio at 0x20122000 {
>
> gpio at 20122000
>
>
Ok
Regards
Padmarao
> > + compatible = "microchip,mpfs-mss-gpio";
> > + interrupt-parent = <&plic>;
> > + interrupts = <13 14 15 16 17 18 19 20 21 22 23
> 24 25 26
> > + 27 28 29 30 31 32 33 34 35 36 37
> 38 39
> > + 40 41 42 43 44>;
> > + gpio-controller;
> > + clocks = <&clkcfg CLK_GPIO2>;
> > + reg = <0x00 0x20122000 0x0 0x1000>;
> > + reg-names = "control";
> > + #gpio-cells = <2>;
> > + status = "disabled";
> > + };
> > + };
> > +};
>
> Regards,
> Bin
>
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