[PATCH v7 01/28] clk: export generic routines

[Dario Binacchi]

Export routines that can be used by other drivers avoiding duplicating
code.

Signed-off-by: Dario Binacchi <dariobin at libero.it>
Reviewed-by: Simon Glass <sjg at chromium.org>

---

(no changes since v2)

Changes in v2:
- Add the clk_ prefix to the divider functions.
- Add kernel-doc comments to the exported functions.

 drivers/clk/clk-divider.c    | 24 +++++++--------
 include/linux/clk-provider.h | 57 ++++++++++++++++++++++++++++++++++++
 2 files changed, 69 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 8f59d7fb72..9df50a5e72 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -28,8 +28,8 @@
 
 #define UBOOT_DM_CLK_CCF_DIVIDER "ccf_clk_divider"
 
-static unsigned int _get_table_div(const struct clk_div_table *table,
-				   unsigned int val)
+unsigned int clk_divider_get_table_div(const struct clk_div_table *table,
+				       unsigned int val)
 {
 	const struct clk_div_table *clkt;
 
@@ -49,7 +49,7 @@ static unsigned int _get_div(const struct clk_div_table *table,
 	if (flags & CLK_DIVIDER_MAX_AT_ZERO)
 		return val ? val : clk_div_mask(width) + 1;
 	if (table)
-		return _get_table_div(table, val);
+		return clk_divider_get_table_div(table, val);
 	return val + 1;
 }
 
@@ -89,8 +89,8 @@ static ulong clk_divider_recalc_rate(struct clk *clk)
 				   divider->flags, divider->width);
 }
 
-static bool _is_valid_table_div(const struct clk_div_table *table,
-				unsigned int div)
+bool clk_divider_is_valid_table_div(const struct clk_div_table *table,
+				    unsigned int div)
 {
 	const struct clk_div_table *clkt;
 
@@ -100,18 +100,18 @@ static bool _is_valid_table_div(const struct clk_div_table *table,
 	return false;
 }
 
-static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
-			  unsigned long flags)
+bool clk_divider_is_valid_div(const struct clk_div_table *table,
+			      unsigned int div, unsigned long flags)
 {
 	if (flags & CLK_DIVIDER_POWER_OF_TWO)
 		return is_power_of_2(div);
 	if (table)
-		return _is_valid_table_div(table, div);
+		return clk_divider_is_valid_table_div(table, div);
 	return true;
 }
 
-static unsigned int _get_table_val(const struct clk_div_table *table,
-				   unsigned int div)
+unsigned int clk_divider_get_table_val(const struct clk_div_table *table,
+				       unsigned int div)
 {
 	const struct clk_div_table *clkt;
 
@@ -131,7 +131,7 @@ static unsigned int _get_val(const struct clk_div_table *table,
 	if (flags & CLK_DIVIDER_MAX_AT_ZERO)
 		return (div == clk_div_mask(width) + 1) ? 0 : div;
 	if (table)
-		return  _get_table_val(table, div);
+		return clk_divider_get_table_val(table, div);
 	return div - 1;
 }
 int divider_get_val(unsigned long rate, unsigned long parent_rate,
@@ -142,7 +142,7 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate,
 
 	div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
 
-	if (!_is_valid_div(table, div, flags))
+	if (!clk_divider_is_valid_div(table, div, flags))
 		return -EINVAL;
 
 	value = _get_val(table, div, flags, width);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 79dce8f0ad..a94539037a 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -76,6 +76,19 @@ struct clk_mux {
 extern const struct clk_ops clk_mux_ops;
 u8 clk_mux_get_parent(struct clk *clk);
 
+/**
+ * clk_mux_index_to_val() - Convert the parent index to the register value
+ *
+ * It returns the value to write in the hardware register to output the selected
+ * input clock parent.
+ *
+ * @table: array of register values corresponding to the parent index (optional)
+ * @flags: hardware-specific flags
+ * @index: parent clock index
+ * @return the register value
+ */
+unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
+
 struct clk_gate {
 	struct clk	clk;
 	void __iomem	*reg;
@@ -125,6 +138,50 @@ struct clk_divider {
 #define CLK_DIVIDER_READ_ONLY		BIT(5)
 #define CLK_DIVIDER_MAX_AT_ZERO		BIT(6)
 extern const struct clk_ops clk_divider_ops;
+
+/**
+ * clk_divider_get_table_div() - convert the register value to the divider
+ *
+ * @table:  array of register values corresponding to valid dividers
+ * @val: value to convert
+ * @return the divider
+ */
+unsigned int clk_divider_get_table_div(const struct clk_div_table *table,
+				       unsigned int val);
+
+/**
+ * clk_divider_get_table_val() - convert the divider to the register value
+ *
+ * It returns the value to write in the hardware register to divide the input
+ * clock rate by @div.
+ *
+ * @table: array of register values corresponding to valid dividers
+ * @div: requested divider
+ * @return the register value
+ */
+unsigned int clk_divider_get_table_val(const struct clk_div_table *table,
+				       unsigned int div);
+
+/**
+ * clk_divider_is_valid_div() - check if the divider is valid
+ *
+ * @table: array of valid dividers (optional)
+ * @div: divider to check
+ * @flags: hardware-specific flags
+ * @return true if the divider is valid, false otherwise
+ */
+bool clk_divider_is_valid_div(const struct clk_div_table *table,
+			      unsigned int div, unsigned long flags);
+
+/**
+ * clk_divider_is_valid_table_div - check if the divider is in the @table array
+ *
+ * @table: array of valid dividers
+ * @div: divider to check
+ * @return true if the divider is found in the @table array, false otherwise
+ */
+bool clk_divider_is_valid_table_div(const struct clk_div_table *table,
+				    unsigned int div);
 unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
 				  unsigned int val,
 				  const struct clk_div_table *table,
-- 
2.17.1