[PATCH] usb: xhci: Use only 32-bit accesses in nvme_writeq/nvme_readq

[Bin Meng]

Hi Stefan,

On Wed, Dec 30, 2020 at 3:37 AM Stefan Agner <stefan at agner.ch> wrote:

The tag is wrong. Should be nvme:

>
> There might be hardware configurations where 64-bit data accesses
> to NVMe registers are not supported properly.  This patch removes
> the readq/writeq so always two 32-bit accesses are used to read/write
> 64-bit NVMe registers, similarly as it is done in Linux kernel.
>
> This patch fixes operation of NVMe devices on RPi4 Broadcom
> BCM2711 SoC based board, where the VL805 USB XHCI controller is
> connected to the PCIe Root Complex, which is attached to the system
> through the SCB bridge.
>
> Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
> the 64-bit wide register accesses initiated by the CPU are not properly
> translated to a sequence of 32-bit PCIe accesses.
> nvme_readq(), for example, always returns same value in upper and lower
> 32-bits, e.g. 0x3c033fff3c033fff which lead to NVMe devices to fail
> probing.
>
> This fix is analogous to commit 8e2ab05000ab ("usb: xhci: Use only
> 32-bit accesses in xhci_writeq/xhci_readq").
>
> Cc: Sylwester Nawrocki <s.nawrocki at samsung.com>
> Cc: Zhikang Zhang <zhikang.zhang at nxp.com>
> Cc: Nicolas Saenz Julienne <nsaenzjulienne at suse.de>
> Cc: Matthias Brugger <mbrugger at suse.com>
> Signed-off-by: Stefan Agner <stefan at agner.ch>
> ---
>
>  drivers/nvme/nvme.h | 8 --------
>  1 file changed, 8 deletions(-)
>

Otherwise, LGTM:

Reviewed-by: Bin Meng <bmeng.cn at gmail.com>