[PATCH v3 07/12] riscv: Add option to support RISC-V privileged spec 1.9.1

[Sean Anderson]

On 2/4/20 6:21 AM, Bin Meng wrote:
> Hi Sean,
> 
> On Mon, Feb 3, 2020 at 4:05 AM Sean Anderson <seanga2 at gmail.com> wrote:
>>
>> Some older processors (notably the Kendryte K210) use an older version of the
>> RISC-V privileged specification. The primary changes between the old and new are
>> in virtual memory, and in the merging of three separate counter enable CSRs.
>> Using the new CSR on an old processor causes an illegal instruction exception.
>> This patch adds an option to use the old CSRs instead of the new one.
>>
>> Signed-off-by: Sean Anderson <seanga2 at gmail.com>
>> ---
>> Changes for v3:
>>   - Renamed from "riscv: Add option to disable writes to mcounteren"
>>   - Added original functionality back for older priv specs.
>> Changes for v2:
>>   - Moved forward in the patch series
>>
>>  arch/riscv/Kconfig           | 10 ++++++++++
>>  arch/riscv/cpu/cpu.c         |  6 ++++++
>>  arch/riscv/include/asm/csr.h |  6 ++++++
>>  3 files changed, 22 insertions(+)
>>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> index 85e15ebffa..87c40f6c4c 100644
>> --- a/arch/riscv/Kconfig
>> +++ b/arch/riscv/Kconfig
>> @@ -222,6 +222,16 @@ config XIP
>>           from a NOR flash memory without copying the code to ram.
>>           Say yes here if U-Boot boots from flash directly.
>>
>> +config RISCV_PRIV_1_9_1
>> +       bool "Use version 1.9.1 of the RISC-V priviledged specification"
> 
> typo: privileged
> 
>> +       help
>> +         Older versions of the RISC-V priviledged specification had
> 
> typo: privileged

Whoops, will fix that for v4.

>> +         separate counter enable CSRs for each privilege mode. Writing
>> +         to the unified mcounteren CSR on a processor implementing the
>> +         old specification will result in an illegal instruction
>> +         exception. In addition to counter CSR changes, the way virtual
>> +         memory is configured was also changed.
>> +
>>  config STACK_SIZE_SHIFT
>>         int
>>         default 14
>> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
>> index e457f6acbf..83cb6557cd 100644
>> --- a/arch/riscv/cpu/cpu.c
>> +++ b/arch/riscv/cpu/cpu.c
>> @@ -89,7 +89,13 @@ int arch_cpu_init_dm(void)
>>                  * Enable perf counters for cycle, time,
>>                  * and instret counters only
>>                  */
>> +#ifdef CONFIG_RISCV_PRIV_1_9_1
>> +               /* FIXME: Can't use the macro for some reason... */
> 
> This is weird ...

I believe the macro compiles to "csrs CSR_FOO". At least with my
gcc/binutils (9.2.0/2.33.1) this style is not available for these older
CSRs. Perhaps it would work if we switched to letting it compile with
the numeric CSR as defined earlier in asm/csr.h

--Sean