[PATCH v3 07/12] riscv: Add option to support RISC-V privileged spec 1.9.1

Sean Anderson seanga2 at gmail.com
Tue Feb 4 15:48:05 CET 2020

On 2/4/20 9:38 AM, Bin Meng wrote:
> Hi Sean,
> On Tue, Feb 4, 2020 at 10:19 PM Sean Anderson <seanga2 at gmail.com> wrote:
>> I believe the macro compiles to "csrs CSR_FOO". At least with my
>> gcc/binutils (9.2.0/2.33.1) this style is not available for these older
>> CSRs. Perhaps it would work if we switched to letting it compile with
>> the numeric CSR as defined earlier in asm/csr.h
> It's already using the numeric CSR for csr_write(). Could you double check?

Well, the current definition is

#define csr_write(csr, val)					\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0"	\
			      : : "rK" (__v)			\
			      : "memory");			\

and _ASM_STR(csr) evaluates to #csr. I think that results in something

__asm__("csrw " "CSR_FOO" ", %0"

In any case, the errors I get are

arch/riscv/cpu/cpu.c: Assembler messages:
arch/riscv/cpu/cpu.c:94: Error: unknown CSR `CSR_MSCOUNTEREN'
arch/riscv/cpu/cpu.c:94: Error: unknown CSR `CSR_MSCOUNTEREN'

which doesn't seem like a numeric CSR to me.


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