[PATCH v3 07/12] riscv: Add option to support RISC-V privileged spec 1.9.1

Sean Anderson seanga2 at gmail.com
Tue Feb 4 17:07:32 CET 2020


On 2/4/20 11:04 AM, Bin Meng wrote:
> Hi Sean,
> 
> On Tue, Feb 4, 2020 at 10:48 PM Sean Anderson <seanga2 at gmail.com> wrote:
>> In any case, the errors I get are
>>
>> arch/riscv/cpu/cpu.c: Assembler messages:
>> arch/riscv/cpu/cpu.c:94: Error: unknown CSR `CSR_MSCOUNTEREN'
>> arch/riscv/cpu/cpu.c:94: Error: unknown CSR `CSR_MSCOUNTEREN'
>>
>> which doesn't seem like a numeric CSR to me.
> 
> Oops, I did a careful look and found that's because 'CSR_MSCOUNTEREN'
> is undefined.
> 
> +#ifdef RISCV_PRIV_1_9_1
> 
> This should be: CONFIG_RISCV_PRIV_1_9_1
> 
> +#define CSR_MUCOUNTEREN         0x320
> +#define CSR_MSCOUNTEREN         0x321
> +#define CSR_MHCOUNTEREN         0x322
> +#else
>  #define CSR_MCOUNTEREN         0x306
> +#endif
> 
> Regards,
> Bin

Ah, good catch, thanks. I'll be sure to fix that for v4.

--Sean



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