[U-Boot Patch v2 0/4] Fix currently available support for flash on HiFive Unleashed

[Sagar Kadam]

Hello Bin,

> -----Original Message-----
> From: Bin Meng <bmeng.cn at gmail.com>
> Sent: Tuesday, February 4, 2020 5:21 PM
> To: Sagar Kadam <sagar.kadam at sifive.com>
> Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Rick Chen
> <rick at andestech.com>; Paul Walmsley ( Sifive) <paul.walmsley at sifive.com>;
> Jagan Teki <jagan at amarulasolutions.com>; Anup Patel
> <anup.patel at wdc.com>
> Subject: Re: [U-Boot Patch v2 0/4] Fix currently available support for flash on
> HiFive Unleashed
> 
> Hi Sagar,
> 
> On Wed, Jan 29, 2020 at 2:02 AM Sagar Shrikant Kadam
> <sagar.kadam at sifive.com> wrote:
> >
> > Currently device ID for flash mounted on HiFive Unleashed is added to
> > U-Boot. Also there are few patches about to go in mainline (Thanks to
> > Jagan Tekki and Bin Meng).
> >
> > This series addresses few issues discussed there:
> > Patch 1:Add num-cs to device tree which is used by spi-uclass to detect
> >         valid chip select numbers
> > Patch 2:Handles valid chip selects only. Flash device is now detected only
> >         on chip select 0.
> > Patch 3:Over-ride spi tx/rx width specified in hifive-unleshed-a00.dts file
> >         from 4 to 1 in corresponding -u-boot.dtsi
> >
> 
> Thank you for fixing all these SPI flash issues!
> 
> > This series is based on mainline commit c05b38df477a ("common: fix
> > regression on block cache init") and two below mentioned patches from
> > [1] [U-Boot,v2,4/5] riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsi
> > [U-Boot,v2,5/5] sifive: fu540: Enable spi-nor flash support
> >
> > [1] https://patchwork.ozlabs.org/patch/1177979/
> >
> > The above series is available for testing here[2] [2]
> > https://github.com/sagsifive/u-boot/tree/dev/sagark/test_spi-nor_v2
> >
> > Change History:
> > V1-V2:
> > 1. Dropped 6th and 7th patch sent in V1 from this series so as to separate
> >    out spi-nor related changes in different series and avoid adding TODO
> >    fixes to spi-nor-core framework.
> 
> Did you resend the 6th and 7th patches as a separate series? I can't find
> them on the ML.
>
Thanks for your review Bin.
I have differed 6th and 7th patches  as of now, as these could be handled 
separately as it contained a TODO part which was not suitable to be introduced 
into the spi-nor framework. So for now, I have added a workaround in the 3rd patch
using which one can a working flash support. 

BR,
Sagar 
> > 2. Removed patch to include -uboot.dts, as it gets automatically included.
> > 3. Over-ride tx/rx width from hifive-unleashed-a00.dts using hifive
> >    -unleashed-a00-u-boot.dtsi
> > 4. Print fdt base address in board info for debugging.
> >
> > V1: First version of series
> >
> >
> > ================Log for reference===================== Flash
> detection
> > only at valid Chip select => sf probe 0:0
> > SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB,
> > total 32 MiB => sf probe 0:1 Invalid cs number = 1 Failed to
> > initialize SPI flash at 0:1 (error -22) => sf probe 0:2 Invalid cs
> > number = 2 Failed to initialize SPI flash at 0:2 (error -22) => sf
> > probe 0:0
> > SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB,
> > total 32 MiB
> >
> > =>----------------------------------------------------------------
> > Full flash memory erase/write/read/validate => mw 0x80600000
> > 0x12348765 0x800000 => sf erase 0x0 0x2000000
> > SF: 33554432 bytes @ 0x0 Erased: OK
> > => sf write 0x80600000 0x0 0x2000000
> > device 0 whole chip
> > SF: 33554432 bytes @ 0x0 Written: OK
> > => sf read  0x82600000 0x0 0x2000000
> > device 0 whole chip
> > SF: 33554432 bytes @ 0x0 Read: OK
> > => cmp.b 0x80600000 0x82600000 0x2000000 Total of 33554432 byte(s)
> > were the same
> > =>----------------------------------------------------------------
> 
> Regards,
> Bin