[PATCH] net: phy: dp83867: Clean force link good bit

[Michal Simek]

On Xilinx ZynqMP revA board initial value of PHYCR register is 0x5448 which
means FORCE_LINK_GOOD is already setup. Origin code was doing write but the
new code is doing read/modify/write and keep this bit untouched. That's why
ethernet stop to work.
The patch is cleaning this bit when PHYCR value is composed.

Tested on Xilinx zcu102-revA and zcu104-rev1.0 boards.

Fixes: 37d6265f2bfa ("net: phy: dp83867: refactor rgmii configuration")
Signed-off-by: Michal Simek <michal.simek at xilinx.com>
---

 drivers/net/phy/dp83867.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index a43793cd4274..4d796e289c45 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -64,6 +64,7 @@
 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT		14
 #define DP83867_PHYCR_FIFO_DEPTH_MASK		GENMASK(15, 14)
 #define DP83867_PHYCR_RESERVED_MASK	BIT(11)
+#define DP83867_PHYCR_FORCE_LINK_GOOD	BIT(10)
 #define DP83867_MDI_CROSSOVER		5
 #define DP83867_MDI_CROSSOVER_MDIX	2
 #define DP83867_PHYCTRL_SGMIIEN			0x0800
@@ -283,6 +284,9 @@ static int dp83867_config(struct phy_device *phydev)
 		val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
 		val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 
+		/* Do not force link good */
+		val &= ~DP83867_PHYCR_FORCE_LINK_GOOD;
+
 		/* The code below checks if "port mirroring" N/A MODE4 has been
 		 * enabled during power on bootstrap.
 		 *
-- 
2.25.0