[PATCH v4 6/6] board: presidio-asic: Add basic G3 engr. development board support
Alex Nemirovsky
Alex.Nemirovsky at cortina-access.com
Fri Feb 7 00:13:51 CET 2020
Hello Tom and Daniel,
This v4 of patch 6/6 in the series is the only one which yield feedback in the prior v3. All other are in “Reviewed-By†state.
We hope that v4 sent out a week ago has addressed those issues.
Let us know if there is anything else holding up the series acceptance.
BR
-AN
> On Jan 30, 2020, at 12:34 PM, Alex Nemirovsky <Alex.Nemirovsky at cortina-access.com> wrote:
>
> Add basic Presidio G3 engineering board support
>
> Signed-off-by: Alex Nemirovsky <alex.nemirovsky at cortina-access.com>
>
> ---
>
> Changes in v4:
> - clean up presidio_asic.h per trini recommendations
> - use autogen savedefconfig instead of manual maintained file
>
> Changes in v3:
> - fixed dts closing bracket indentation
> - presidio.h: remove deadcode from presidio.h
> - presidio.h: remove CA_REG_READ/CA_REG_WRITE wrapper macros
> - presidio.h: remove CA77xx define replace use CA common Kconfig
> SoC selection instead
> - select SOC_CA7774 via board's Kconfig
> - select BIT64 via board's Kconfig instead of presidio.h
>
> Changes in v2: None
>
> arch/arm/Kconfig | 5 +
> arch/arm/dts/Makefile | 2 +
> arch/arm/dts/ca-presidio-engboard.dts | 69 ++++++++++++++
> arch/arm/mach-cortina/Makefile | 5 +
> board/cortina/presidio-asic/Kconfig | 18 ++++
> board/cortina/presidio-asic/MAINTAINERS | 6 ++
> board/cortina/presidio-asic/Makefile | 8 ++
> board/cortina/presidio-asic/lowlevel_init.S | 87 +++++++++++++++++
> board/cortina/presidio-asic/presidio.c | 134 +++++++++++++++++++++++++++
> configs/cortina_presidio-asic-base_defconfig | 29 ++++++
> include/configs/presidio_asic.h | 75 +++++++++++++++
> 11 files changed, 438 insertions(+)
> create mode 100644 arch/arm/dts/ca-presidio-engboard.dts
> create mode 100644 arch/arm/mach-cortina/Makefile
> create mode 100644 board/cortina/presidio-asic/Kconfig
> create mode 100644 board/cortina/presidio-asic/MAINTAINERS
> create mode 100644 board/cortina/presidio-asic/Makefile
> create mode 100644 board/cortina/presidio-asic/lowlevel_init.S
> create mode 100644 board/cortina/presidio-asic/presidio.c
> create mode 100644 configs/cortina_presidio-asic-base_defconfig
> create mode 100644 include/configs/presidio_asic.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 36c9c2f..6d95cde 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1638,6 +1638,10 @@ config TARGET_DURIAN
> Support for durian platform.
> It has 2GB Sdram, uart and pcie.
>
> +config TARGET_PRESIDIO_ASIC
> + bool "Support Cortina Presidio ASIC Platform"
> + select ARM64
> +
> endchoice
>
> config ARCH_SUPPORT_TFABOOT
> @@ -1782,6 +1786,7 @@ source "board/Marvell/gplugd/Kconfig"
> source "board/armadeus/apf27/Kconfig"
> source "board/armltd/vexpress/Kconfig"
> source "board/armltd/vexpress64/Kconfig"
> +source "board/cortina/presidio-asic/Kconfig"
> source "board/broadcom/bcm23550_w1d/Kconfig"
> source "board/broadcom/bcm28155_ap/Kconfig"
> source "board/broadcom/bcm963158/Kconfig"
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 0127a91..81db1e6 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -849,6 +849,8 @@ dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb
>
> dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
>
> +dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
> +
> targets += $(dtb-y)
>
> # Add any required device tree compiler flags here
> diff --git a/arch/arm/dts/ca-presidio-engboard.dts b/arch/arm/dts/ca-presidio-engboard.dts
> new file mode 100644
> index 0000000..c03dacc
> --- /dev/null
> +++ b/arch/arm/dts/ca-presidio-engboard.dts
> @@ -0,0 +1,69 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2020, Cortina Access Inc.
> + */
> +
> +/dts-v1/;
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + mmc0: mmc at f4400000 {
> + compatible = "snps,dw-cortina";
> + reg = <0x0 0xf4400000 0x1000>;
> + bus-width = <4>;
> + io_ds = <0x77>;
> + fifo-mode;
> + sd_dll_ctrl = <0xf43200e8>;
> + io_drv_ctrl = <0xf432004c>;
> + };
> +
> + gpio0: gpio-controller at 0xf4329280 {
> + compatible = "cortina,ca-gpio";
> + reg = <0x0 0xf4329280 0x24>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "okay";
> + };
> + gpio1: gpio-controller at 0xf43292a4 {
> + compatible = "cortina,ca-gpio";
> + reg = <0x0 0xf43292a4 0x24>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + watchdog: watchdog at 0xf432901c {
> + compatible = "cortina,ca-wdt";
> + reg = <0x0 0xf432901c 0x34>,
> + <0x0 0xf4320020 0x04>;
> + status = "okay";
> + };
> +
> + uart0: serial at 0xf4329148 {
> + u-boot,dm-pre-reloc;
> + compatible = "cortina,ca-uart";
> + reg = <0x0 0xf4329148 0x30>;
> + status = "okay";
> + };
> +
> + i2c: i2c at f4329120 {
> + compatible = "cortina,ca-i2c";
> + reg = <0x0 0xf4329120 0x28>;
> + clock-frequency = <400000>;
> + };
> +
> + sflash: sflash-controller at f4324000 {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + compatible = "cortina,ca-sflash";
> + reg = <0x0 0xf4324000 0x50>;
> + reg-names = "sflash-regs";
> + flash at 0 {
> + compatible = "jedec,spi-nor";
> + spi-rx-bus-width = <1>;
> + spi-max-frequency = <108000000>;
> + };
> + };
> +};
> diff --git a/arch/arm/mach-cortina/Makefile b/arch/arm/mach-cortina/Makefile
> new file mode 100644
> index 0000000..ffb8692
> --- /dev/null
> +++ b/arch/arm/mach-cortina/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# (C) Copyright 2020 Cortina Access Inc.
> +#
> +obj-y += lowlevel_init.o
> diff --git a/board/cortina/presidio-asic/Kconfig b/board/cortina/presidio-asic/Kconfig
> new file mode 100644
> index 0000000..8e6f6cf
> --- /dev/null
> +++ b/board/cortina/presidio-asic/Kconfig
> @@ -0,0 +1,18 @@
> +if TARGET_PRESIDIO_ASIC
> +config BIT64
> + bool
> + default y
> +
> +select SOC_CA7774
> +
> +config SYS_BOARD
> + default "presidio-asic"
> +
> +config SYS_VENDOR
> + default "cortina"
> +
> +config SYS_CONFIG_NAME
> + default "presidio_asic"
> +
> +source "board/cortina/common/Kconfig"
> +endif
> diff --git a/board/cortina/presidio-asic/MAINTAINERS b/board/cortina/presidio-asic/MAINTAINERS
> new file mode 100644
> index 0000000..9db17bd
> --- /dev/null
> +++ b/board/cortina/presidio-asic/MAINTAINERS
> @@ -0,0 +1,6 @@
> +Cortina Presidio ASIC G3 Engineering BOARD
> +M: Alex Nemirovsky <alex.nemirovsky at cortina-access.com>
> +S: Supported
> +F: board/cortina/presidio-asic/
> +F: include/configs/presidio_asic.h
> +F: configs/cortina_presidio-asic*defconfig
> diff --git a/board/cortina/presidio-asic/Makefile b/board/cortina/presidio-asic/Makefile
> new file mode 100644
> index 0000000..d167a15
> --- /dev/null
> +++ b/board/cortina/presidio-asic/Makefile
> @@ -0,0 +1,8 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# (C) Copyright 2020 Cortina-Access.Inc.
> +#
> +#
> +
> +obj-y := presidio.o
> +obj-y += lowlevel_init.o
> diff --git a/board/cortina/presidio-asic/lowlevel_init.S b/board/cortina/presidio-asic/lowlevel_init.S
> new file mode 100644
> index 0000000..4450a5d
> --- /dev/null
> +++ b/board/cortina/presidio-asic/lowlevel_init.S
> @@ -0,0 +1,87 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2020 Cortina-Access
> + *
> + */
> +
> +
> +#include <asm-offsets.h>
> +#include <config.h>
> +#include <linux/linkage.h>
> +#include <asm/macro.h>
> +#include <asm/armv8/mmu.h>
> +
> + .globl lowlevel_init
> +lowlevel_init:
> + mov x29, lr /* Save LR */
> +
> +#if defined(CONFIG_SOC_CA7774)
> + /* Enable SMPEN in CPUECTLR */
> + mrs x0, s3_1_c15_c2_1
> + tst x0, #0x40
> + b.ne skip_smp_setup
> + orr x0, x0, #0x40
> + msr s3_1_c15_c2_1, x0
> +skip_smp_setup:
> +#endif
> +
> +#if defined(CONFIG_SOC_CA8277B)
> + /* Enable CPU Timer */
> + ldr x0, =CONFIG_SYS_TIMER_BASE
> + mov x1, #1
> + str w1, [x0]
> +#endif
> +
> +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
> + branch_if_slave x0, 1f
> +#ifndef CONFIG_TARGET_VENUS
> + ldr x0, =GICD_BASE
> + bl gic_init_secure
> +#endif
> +1:
> +#if defined(CONFIG_GICV3)
> + ldr x0, =GICR_BASE
> + bl gic_init_secure_percpu
> +#elif defined(CONFIG_GICV2)
> + ldr x0, =GICD_BASE
> + ldr x1, =GICC_BASE
> + bl gic_init_secure_percpu
> +#endif
> +#endif
> +
> +#ifdef CONFIG_ARMV8_MULTIENTRY
> + branch_if_master x0, x1, 2f
> +
> + /*
> + * Slave should wait for master clearing spin table.
> + * This sync prevent salves observing incorrect
> + * value of spin table and jumping to wrong place.
> + */
> +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
> +#ifdef CONFIG_GICV2
> + ldr x0, =GICC_BASE
> +#endif
> + bl gic_wait_for_interrupt
> +#endif
> +
> + /*
> + * All slaves will enter EL2 and optionally EL1.
> + */
> + adr x4, lowlevel_in_el2
> + ldr x5, =ES_TO_AARCH64
> + bl armv8_switch_to_el2
> +
> +lowlevel_in_el2:
> +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
> + adr x4, lowlevel_in_el1
> + ldr x5, =ES_TO_AARCH64
> + bl armv8_switch_to_el1
> +
> +lowlevel_in_el1:
> +#endif
> +
> +#endif /* CONFIG_ARMV8_MULTIENTRY */
> +
> +2:
> + mov lr, x29 /* Restore LR */
> + ret
> diff --git a/board/cortina/presidio-asic/presidio.c b/board/cortina/presidio-asic/presidio.c
> new file mode 100644
> index 0000000..b4fa01f
> --- /dev/null
> +++ b/board/cortina/presidio-asic/presidio.c
> @@ -0,0 +1,134 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2020 - Cortina Access Inc.
> + *
> + */
> +#include <common.h>
> +#include <malloc.h>
> +#include <errno.h>
> +#include <netdev.h>
> +#include <asm/io.h>
> +#include <linux/compiler.h>
> +#include <configs/presidio_asic.h>
> +#include <linux/psci.h>
> +#include <asm/psci.h>
> +#include <cpu_func.h>
> +#include <asm/armv8/mmu.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define CA_PERIPH_BASE 0xE0000000UL
> +#define CA_PERIPH_SIZE 0x20000000UL
> +#define CA_GLOBAL_BASE 0xf4320000
> +#define CA_GLOBAL_JTAG_ID 0xf4320000
> +#define CA_GLOBAL_BLOCK_RESET 0xf4320004
> +#define CA_GLOBAL_BLOCK_RESET_RESET_DMA BIT(16)
> +#define CA_DMA_SEC_SSP_BAUDRATE_CTRL 0xf7001b94
> +#define CA_DMA_SEC_SSP_ID 0xf7001b80
> +
> +int print_cpuinfo(void)
> +{
> + printf("CPU: Cortina Presidio G3\n");
> + return 0;
> +}
> +
> +static struct mm_region presidio_mem_map[] = {
> + {
> + .virt = DDR_BASE,
> + .phys = DDR_BASE,
> + .size = PHYS_SDRAM_1_SIZE,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_OUTER_SHARE
> + },
> + {
> + .virt = CA_PERIPH_BASE,
> + .phys = CA_PERIPH_BASE,
> + .size = CA_PERIPH_SIZE,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE
> + },
> + {
> + /* List terminator */
> + 0,
> + }
> +};
> +
> +struct mm_region *mem_map = presidio_mem_map;
> +
> +static noinline int invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1,
> + u64 arg2)
> +{
> + asm volatile("mov x0, %0\n"
> + "mov x1, %1\n"
> + "mov x2, %2\n"
> + "mov x3, %3\n"
> + "smc #0\n"
> + : "+r" (function_id)
> + : "r" (arg0), "r" (arg1), "r" (arg2)
> + );
> +
> + return function_id;
> +}
> +
> +int board_early_init_r(void)
> +{
> + dcache_disable();
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + unsigned int reg_data, jtag_id;
> +
> + /* Enable timer */
> + writel(1, CONFIG_SYS_TIMER_BASE);
> +
> + /* Enable snoop in CCI400 slave port#4 */
> + writel(3, 0xF5595000);
> +
> + jtag_id = readl(CA_GLOBAL_JTAG_ID);
> +
> + /* If this is HGU variant then do not use
> + * the Saturn daughter card ref. clk
> + */
> + if (jtag_id == 0x1010D8F3) {
> + reg_data = readl(0xF3100064);
> + /* change multifunc. REF CLK pin to
> + * a simple GPIO pin
> + */
> + reg_data |= (1 << 1);
> + writel(reg_data, 0xf3100064);
> + }
> +
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + unsigned int ddr_size;
> +
> + ddr_size = readl(0x111100c);
> + gd->ram_size = ddr_size * 0x100000;
> + return 0;
> +}
> +
> +void reset_cpu(ulong addr)
> +{
> + invoke_psci_fn_smc(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0);
> +}
> +
> +#ifdef CONFIG_LAST_STAGE_INIT
> +int last_stage_init(void)
> +{
> + u32 val;
> +
> + val = readl(CA_GLOBAL_BLOCK_RESET);
> + val &= ~CA_GLOBAL_BLOCK_RESET_RESET_DMA;
> + writel(val, CA_GLOBAL_BLOCK_RESET);
> +
> + /* reduce output pclk ~3.7Hz to save power consumption */
> + writel(0x000000FF, CA_DMA_SEC_SSP_BAUDRATE_CTRL);
> +
> + return 0;
> +}
> +#endif
> diff --git a/configs/cortina_presidio-asic-base_defconfig b/configs/cortina_presidio-asic-base_defconfig
> new file mode 100644
> index 0000000..ec64bd2
> --- /dev/null
> +++ b/configs/cortina_presidio-asic-base_defconfig
> @@ -0,0 +1,29 @@
> +CONFIG_ARM=y
> +# CONFIG_SYS_ARCH_TIMER is not set
> +CONFIG_TARGET_PRESIDIO_ASIC=y
> +CONFIG_SYS_TEXT_BASE=0x04000000
> +CONFIG_DM_GPIO=y
> +CONFIG_ENV_SIZE=0x20000
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_IDENT_STRING="Presidio-SoC"
> +CONFIG_SHOW_BOOT_PROGRESS=y
> +CONFIG_BOOTDELAY=3
> +CONFIG_USE_BOOTARGS=y
> +CONFIG_BOOTARGS="earlycon=serial,0xf4329148 console=ttyS0,115200 root=/dev/ram0"
> +CONFIG_BOARD_EARLY_INIT_R=y
> +CONFIG_SYS_PROMPT="G3#"
> +CONFIG_CMD_WDT=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_TIMER=y
> +CONFIG_CMD_SMC=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_OF_LIVE=y
> +CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
> +# CONFIG_NET is not set
> +CONFIG_DM=y
> +CONFIG_CORTINA_GPIO=y
> +# CONFIG_MMC is not set
> +CONFIG_DM_SERIAL=y
> +CONFIG_CORTINA_UART=y
> +CONFIG_WDT=y
> +CONFIG_WDT_CORTINA=y
> diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h
> new file mode 100644
> index 0000000..023092e
> --- /dev/null
> +++ b/include/configs/presidio_asic.h
> @@ -0,0 +1,75 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2020 Cortina Access Inc.
> + *
> + * Configuration for Cortina-Access Presidio board.
> + */
> +
> +#ifndef __PRESIDIO_ASIC_H
> +#define __PRESIDIO_ASIC_H
> +
> +#define CONFIG_REMAKE_ELF
> +
> +#define CONFIG_SUPPORT_RAW_INITRD
> +
> +#define CONFIG_SYS_INIT_SP_ADDR 0x00100000
> +#define CONFIG_SYS_BOOTM_LEN 0x00c00000
> +
> +/* Generic Timer Definitions */
> +#define COUNTER_FREQUENCY 25000000
> +#define CONFIG_SYS_TIMER_RATE COUNTER_FREQUENCY
> +#define CONFIG_SYS_TIMER_COUNTER 0xf4321008
> +
> +/* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
> + * does not yet support DT. Thus define it here.
> + */
> +#define CONFIG_GICV2
> +#define GICD_BASE 0xf7011000
> +#define GICC_BASE 0xf7012000
> +
> +#define CONFIG_SYS_MEMTEST_SCRATCH 0x00100000
> +#define CONFIG_SYS_MEMTEST_START 0x05000000
> +#define CONFIG_SYS_MEMTEST_END 0x0D000000
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
> +
> +#define CONFIG_SYS_TIMER_BASE 0xf4321000
> +
> +/* Use external clock source */
> +#define PRESIDIO_APB_CLK 125000000
> +#define CORTINA_PER_IO_FREQ PRESIDIO_APB_CLK
> +
> +/* Cortina Serial Configuration */
> +#define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK)
> +#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \
> + (void *)CONFIG_SYS_SERIAL1}
> +
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_SERIAL0 PER_UART0_CFG
> +#define CONFIG_SYS_SERIAL1 PER_UART1_CFG
> +
> +/* BOOTP options */
> +#define CONFIG_BOOTP_BOOTFILESIZE
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_LOAD_ADDR (DDR_BASE + 0x10000000)
> +#define CONFIG_LAST_STAGE_INIT
> +
> +/* SDRAM Bank #1 */
> +#define DDR_BASE 0x00000000
> +#define PHYS_SDRAM_1 DDR_BASE
> +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
> +
> +/* Console I/O Buffer Size */
> +#define CONFIG_SYS_CBSIZE 256
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +/* max command args */
> +#define CONFIG_SYS_MAXARGS 64
> +#define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0"
> +
> +#endif /* __PRESIDIO_ASIC_H */
> --
> 2.7.4
>
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