imx8m: composite clock wrong clock parent ?
peng.fan at nxp.com
Tue Feb 18 01:56:04 CET 2020
> Subject: imx8m: composite clock wrong clock parent ?
> I am working on a i.MX8MM based board and I got issue to make the
> Ethernet phy work.
> I noticed that the MDIO clock is not configured properly and the FEC outputs a
> 26,6MHz MDIO clock.
> That's because the clk_get_rate() call at line 1389 returns 24MHz whereas it
> should returns 266MHz as it is set in the device tree and configured in the
> BIOS> md.l 0x30388880 1
> 30388880: 11000000
> With some debug traces we can see that the enet_axi's parent is wrong:
> fecmxc_probe 1388
> clk_get_rate 447: clk clock-controller at 30380000 clk_get_rate 447: clk
> enet1_root_clk clk_get_rate 447: clk enet_axi clk_get_parent_rate 489: clk
> enet_axi parent clock-osc-24m clk_get_parent_rate 489: clk enet1_root_clk
> parent enet_axi fecmxc_probe 1390
> Is this a known issue ?
There is an issue in current clk framework in U-Boot, it could not runtime
set the parent of a clk, and I have not find time to work on this.
I not check whether your issue is related the upper issue in CCF.
> Sébastien Szymanski, Armadeus Systems
> Software engineer
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