[PATCH 03/18] clk: imx: clk-imxrt1050: setup PLL5 for video in non-SPL

[Fabio Estevam]

Hi Giulio,

On Wed, Feb 26, 2020 at 3:16 PM Giulio Benetti
<giulio.benetti at benettiengineering.com> wrote:

> Oh, I've seen now, need to study it before, but now in my mind it's
> getting more clear how that works. But will this work even if shrinked
> CCF in u-boot can't set parent clocks(at least this is what I've

I haven't checked whether 'assigned-clock-parents' works in U-Boot.

> understood)? I mean, basically here for LCDIF I see that only last
> divider get set for achieving pixel-clock, while all parents are get
> only to recalcute the "last divider parent clock".
>
> Also, I can't understand, is it ok setting PLL5 to 650Mhz and un-bypass
> it? The problem is only about clk_set_parent() for LCDIF?

The problem I saw was about hard coding the parent of LCDIF inside the
clock driver.

> Because if a peripheral would set a PLL5 frequency and another
> peripheral use it as parent, then it would set it again.

Yes, but if we leave the correct clock parent decision to be made in
the board dts, we are safe.