[PATCH 3/3] riscv: sifive: fu540: add SPL configuration
Pragnesh Patel
pragnesh.patel at sifive.com
Mon Jan 6 11:08:41 CET 2020
>-----Original Message-----
>From: Jagan Teki <jagan at amarulasolutions.com>
>Sent: 02 January 2020 10:29
>To: Pragnesh Patel <pragnesh.patel at sifive.com>
>Cc: U-Boot-Denx <u-boot at lists.denx.de>; Palmer Dabbelt ( Sifive)
><palmer at sifive.com>; Atish Patra <atish.patra at wdc.com>; Alexander Graf
><agraf at csgraf.de>; Boris Brezillon <bbrezillon at kernel.org>; Rick Chen
><rick at andestech.com>; Anup Patel <Anup.Patel at wdc.com>
>Subject: Re: [PATCH 3/3] riscv: sifive: fu540: add SPL configuration
>
>+ Rick, Anup
>
>Thanks for the patch, scratching my head to get SPL running on this board.
>
>On Tue, Dec 31, 2019 at 7:30 PM Pragnesh Patel
><pragnesh.patel at sifive.com> wrote:
>>
>> This patch provides sifive_fu540_spl_defconfig which can support
>> U-boot SPL to boot from L2 LIM (0x0800_0000) and then boot FIT
>> image including OpenSBI FW_DYNAMIC firmware and U-Boot proper
>> images from MMC boot devices.
>>
>> With sifive_fu540_spl_defconfig:
>>
>> U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
>> u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
>> image u-boot.itb from SD card (replace fw_payload.bin with u-boot.itb)
>> into RAM.
>>
>> SPL related code is leverage from FSBL
>> (https://github.com/sifive/freedom-u540-c000-bootloader.git)
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
>> ---
>> arch/riscv/cpu/u-boot-spl.lds | 1 +
>> arch/riscv/dts/fu540-c000-u-boot.dtsi | 65 +
>> .../dts/hifive-unleashed-a00-u-boot.dtsi | 24 +
>> arch/riscv/include/asm/csr.h | 2 +
>> board/sifive/fu540/Kconfig | 8 +
>> board/sifive/fu540/MAINTAINERS | 1 +
>> board/sifive/fu540/Makefile | 6 +
>> board/sifive/fu540/ememoryotp.c | 143 ++
>> board/sifive/fu540/fu540.c | 31 +-
>> board/sifive/fu540/include/ccache.h | 47 +
>> board/sifive/fu540/include/clkutils.h | 75 +
>> board/sifive/fu540/include/ddrregs.h | 622 +++++++++
>> board/sifive/fu540/include/ememoryotp.h | 24 +
>> board/sifive/fu540/include/fu540-memory-map.h | 427 ++++++
>> board/sifive/fu540/include/i2c.h | 49 +
>> board/sifive/fu540/include/regconfig-ctl.h | 274 ++++
>> board/sifive/fu540/include/regconfig-phy.h | 1224 +++++++++++++++++
>> board/sifive/fu540/include/spi.h | 233 ++++
>> board/sifive/fu540/include/uart.h | 54 +
>> board/sifive/fu540/include/ux00ddr.h | 268 ++++
>> board/sifive/fu540/include/ux00prci.h | 206 +++
>> board/sifive/fu540/spl.c | 321 +++++
>> board/sifive/fu540/uart.c | 64 +
>> configs/sifive_fu540_spl_defconfig | 23 +
>> include/configs/sifive-fu540.h | 17 +
>> lib/Makefile | 1 +
>
>This patch need to divide into multiple patches since it has multiple
>functionalities all in one which indeed difficult for review and not
>good to go for merging.
Will spilt this into multiple patches in v2. Thanks for the suggestion.
>
>> 26 files changed, 4209 insertions(+), 1 deletion(-)
>> create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi
>> create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> create mode 100644 board/sifive/fu540/ememoryotp.c
>> create mode 100644 board/sifive/fu540/include/ccache.h
>> create mode 100644 board/sifive/fu540/include/clkutils.h
>> create mode 100644 board/sifive/fu540/include/ddrregs.h
>> create mode 100644 board/sifive/fu540/include/ememoryotp.h
>> create mode 100644 board/sifive/fu540/include/fu540-memory-map.h
>> create mode 100644 board/sifive/fu540/include/i2c.h
>> create mode 100644 board/sifive/fu540/include/regconfig-ctl.h
>> create mode 100644 board/sifive/fu540/include/regconfig-phy.h
>> create mode 100644 board/sifive/fu540/include/spi.h
>> create mode 100644 board/sifive/fu540/include/uart.h
>> create mode 100644 board/sifive/fu540/include/ux00ddr.h
>> create mode 100644 board/sifive/fu540/include/ux00prci.h
>> create mode 100644 board/sifive/fu540/spl.c
>> create mode 100644 board/sifive/fu540/uart.c
>> create mode 100644 configs/sifive_fu540_spl_defconfig
>>
>> diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
>> index 955dd3106d..d0495ce248 100644
>> --- a/arch/riscv/cpu/u-boot-spl.lds
>> +++ b/arch/riscv/cpu/u-boot-spl.lds
>> @@ -72,6 +72,7 @@ SECTIONS
>> . = ALIGN(4);
>>
>> _end = .;
>> + _image_binary_end = .;
>>
>> .bss : {
>> __bss_start = .;
>> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-
>c000-u-boot.dtsi
>> new file mode 100644
>> index 0000000000..b86cdfb38d
>> --- /dev/null
>> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> @@ -0,0 +1,65 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * (C) Copyright 2019 SiFive, Inc
>> + */
>> +
>> +/ {
>> + cpus {
>> + u-boot,dm-spl;
>> + cpu0: cpu at 0 {
>> + u-boot,dm-spl;
>> + status = "okay";
>> + cpu0_intc: interrupt-controller {
>> + u-boot,dm-spl;
>> + };
>> + };
>> + cpu1: cpu at 1 {
>> + u-boot,dm-spl;
>> + cpu1_intc: interrupt-controller {
>> + u-boot,dm-spl;
>> + };
>> + };
>> + cpu2: cpu at 2 {
>> + u-boot,dm-spl;
>> + cpu2_intc: interrupt-controller {
>> + u-boot,dm-spl;
>> + };
>> + };
>> + cpu3: cpu at 3 {
>> + u-boot,dm-spl;
>> + cpu3_intc: interrupt-controller {
>> + u-boot,dm-spl;
>> + };
>> + };
>> + cpu4: cpu at 4 {
>> + u-boot,dm-spl;
>> + cpu4_intc: interrupt-controller {
>> + u-boot,dm-spl;
>> + };
>> + };
>> + };
>> +
>> + soc {
>> + u-boot,dm-spl;
>> + clint at 2000000 {
>> + compatible = "riscv,clint0";
>> + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 >;
>> + reg = <0x0 0x2000000 0x0 0xc0000>;
>> + u-boot,dm-spl;
>> + };
>> +
>> + };
>> +
>> +};
>> +
>> +&prci {
>> + u-boot,dm-spl;
>> +};
>> +
>> +&uart0 {
>> + u-boot,dm-spl;
>> +};
>> +
>> +&qspi2 {
>> + u-boot,dm-spl;
>> +};
>> diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> new file mode 100644
>> index 0000000000..9b59f4ee14
>> --- /dev/null
>> +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> @@ -0,0 +1,24 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) 2019 SiFive, Inc
>> + */
>> +
>> +#include "fu540-c000-u-boot.dtsi"
>> +
>> +/ {
>> + hfclk {
>> + u-boot,dm-spl;
>> + };
>> +
>> + rtcclk {
>> + u-boot,dm-spl;
>> + };
>> +};
>> +
>> +&qspi2 {
>> +
>> + mmc at 0 {
>> + u-boot,dm-spl;
>> + };
>> +
>> +};
>> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
>> index d1520743a2..125c05dd8a 100644
>> --- a/arch/riscv/include/asm/csr.h
>> +++ b/arch/riscv/include/asm/csr.h
>> @@ -103,6 +103,8 @@
>> #define CSR_TIMEH 0xc81
>> #define CSR_INSTRETH 0xc82
>> #define CSR_MHARTID 0xf14
>> +#define CSR_MCYCLE 0xb00
>> +#define CSR_MCYCLEH 0xb80
>>
>> #ifndef __ASSEMBLY__
>>
>> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
>> index 816a135b21..ac7c6bff37 100644
>> --- a/board/sifive/fu540/Kconfig
>> +++ b/board/sifive/fu540/Kconfig
>> @@ -16,12 +16,20 @@ config SYS_SOC
>> default "fu540"
>>
>> config SYS_TEXT_BASE
>> + default 0x80200000 if SPL
>> default 0x80000000 if !RISCV_SMODE
>> default 0x80200000 if RISCV_SMODE
>>
>> +config SPL_TEXT_BASE
>> + default 0x08000000
>> +
>> +config SPL_OPENSBI_LOAD_ADDR
>> + default 0x80000000
>> +
>> config BOARD_SPECIFIC_OPTIONS # dummy
>> def_bool y
>> select GENERIC_RISCV
>> + select SUPPORT_SPL
>> imply CMD_DHCP
>> imply CMD_EXT2
>> imply CMD_EXT4
>> diff --git a/board/sifive/fu540/MAINTAINERS
>b/board/sifive/fu540/MAINTAINERS
>> index 702d803ad8..42c3f3deb0 100644
>> --- a/board/sifive/fu540/MAINTAINERS
>> +++ b/board/sifive/fu540/MAINTAINERS
>> @@ -7,3 +7,4 @@ S: Maintained
>> F: board/sifive/fu540/
>> F: include/configs/sifive-fu540.h
>> F: configs/sifive_fu540_defconfig
>> +F: configs/sifive_fu540_spl_defconfig
>> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
>> index 6e1862c475..e532beb9d5 100644
>> --- a/board/sifive/fu540/Makefile
>> +++ b/board/sifive/fu540/Makefile
>> @@ -3,3 +3,9 @@
>> # Copyright (c) 2019 Western Digital Corporation or its affiliates.
>>
>> obj-y += fu540.o
>> +
>> +ifdef CONFIG_SPL_BUILD
>> +obj-y += spl.o
>> +obj-y += ememoryotp.o
>> +obj-y += uart.o
>> +endif
>> diff --git a/board/sifive/fu540/ememoryotp.c
>b/board/sifive/fu540/ememoryotp.c
>> new file mode 100644
>> index 0000000000..994724af37
>> --- /dev/null
>> +++ b/board/sifive/fu540/ememoryotp.c
>> @@ -0,0 +1,143 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (c) 2019 SiFive, Inc
>> + *
>> + * Authors:
>> + * Pragnesh Patel <pragnesh.patel at sifive.com>
>> + * Troy Benjegerdes <troy.benjegerdes at sifive.com>
>> + */
>> +
>> +#include <stdint.h>
>> +#include "include/fu540-memory-map.h"
>> +#include "include/clkutils.h"
>> +#include "include/ememoryotp.h"
>> +
>> +#define max(x, y) ((x) > (y) ? (x) : (y))
>> +
>> +extern inline void clkutils_delay_ns(int delay_ns);
>> +
>> +void ememory_otp_power_up_sequence(void)
>> +{
>> + // Probably don't need to do this, since
>> + // all the other stuff has been happening.
>> + // But it is on the wave form.
>> + clkutils_delay_ns(EMEMORYOTP_MIN_TVDS * 1000);
>> +
>> + EMEMORYOTP_REG(EMEMORYOTP_PDSTB) = 1;
>> + clkutils_delay_ns(EMEMORYOTP_MIN_TSAS * 1000);
>> +
>> + EMEMORYOTP_REG(EMEMORYOTP_PTRIM) = 1;
>> + clkutils_delay_ns(EMEMORYOTP_MIN_TTAS * 1000);
>> +}
>> +
>> +void ememory_otp_power_down_sequence(void)
>> +{
>> + clkutils_delay_ns(EMEMORYOTP_MIN_TTAH * 1000);
>> + EMEMORYOTP_REG(EMEMORYOTP_PTRIM) = 0;
>> + clkutils_delay_ns(EMEMORYOTP_MIN_TASH * 1000);
>> + EMEMORYOTP_REG(EMEMORYOTP_PDSTB) = 0;
>> + // No delay indicated after this
>> +}
>> +
>> +void ememory_otp_begin_read(void)
>> +{
>> + // Initialize
>> + EMEMORYOTP_REG(EMEMORYOTP_PCLK) = 0;
>> + EMEMORYOTP_REG(EMEMORYOTP_PA) = 0;
>> + EMEMORYOTP_REG(EMEMORYOTP_PDIN) = 0;
>> + EMEMORYOTP_REG(EMEMORYOTP_PWE) = 0;
>> + EMEMORYOTP_REG(EMEMORYOTP_PTM) = 0;
>> + clkutils_delay_ns(EMEMORYOTP_MIN_TMS * 1000);
>> +
>> + // Enable chip select
>> +
>> + EMEMORYOTP_REG(EMEMORYOTP_PCE) = 1;
>> + clkutils_delay_ns(EMEMORYOTP_MIN_TCS * 1000);
>> +}
>> +
>> +void ememory_otp_exit_read(void)
>> +{
>> + EMEMORYOTP_REG(EMEMORYOTP_PCLK) = 0;
>> + EMEMORYOTP_REG(EMEMORYOTP_PA) = 0;
>> + EMEMORYOTP_REG(EMEMORYOTP_PDIN) = 0;
>> + EMEMORYOTP_REG(EMEMORYOTP_PWE) = 0;
>> + // Disable chip select
>> + EMEMORYOTP_REG(EMEMORYOTP_PCE) = 0;
>> + // Wait before changing PTM
>> + clkutils_delay_ns(EMEMORYOTP_MIN_TMH * 1000);
>> +}
>> +
>> +unsigned int ememory_otp_read(int address)
>> +{
>> + unsigned int read_value;
>> +
>> + EMEMORYOTP_REG(EMEMORYOTP_PA) = address;
>> + // Toggle clock
>> + clkutils_delay_ns(EMEMORYOTP_MIN_TAS * 1000);
>> + EMEMORYOTP_REG(EMEMORYOTP_PCLK) = 1;
>> + // Insert delay until data is ready.
>> + // There are lots of delays
>> + // on the chart, but I think this is the most relevant.
>> + int delay = max(EMEMORYOTP_MAX_TCD, EMEMORYOTP_MIN_TKH);
>> +
>> + clkutils_delay_ns(delay * 1000);
>> + EMEMORYOTP_REG(EMEMORYOTP_PCLK) = 0;
>> + read_value = EMEMORYOTP_REG(EMEMORYOTP_PDOUT);
>> + // Could check here for things like TCYC < TAH + TCD
>> + return read_value;
>> +}
>> +
>> +void ememory_otp_pgm_entry(void)
>> +{
>> + EMEMORYOTP_REG(EMEMORYOTP_PCLK) = 0;
>> + EMEMORYOTP_REG(EMEMORYOTP_PA) = 0;
>> + EMEMORYOTP_REG(EMEMORYOTP_PAS) = 0;
>> + EMEMORYOTP_REG(EMEMORYOTP_PAIO) = 0;
>> + EMEMORYOTP_REG(EMEMORYOTP_PDIN) = 0;
>> + EMEMORYOTP_REG(EMEMORYOTP_PWE) = 0;
>> + EMEMORYOTP_REG(EMEMORYOTP_PTM) = 2;
>> + clkutils_delay_ns(EMEMORYOTP_MIN_TMS * 1000);
>> + EMEMORYOTP_REG(EMEMORYOTP_PCE) = 1;
>> + clkutils_delay_ns(EMEMORYOTP_TYP_TCSP * 1000);
>> + EMEMORYOTP_REG(EMEMORYOTP_PPROG) = 1;
>> + clkutils_delay_ns(EMEMORYOTP_TYP_TPPS * 1000);
>> + EMEMORYOTP_REG(EMEMORYOTP_PTRIM) = 1;
>> +}
>> +
>> +void ememory_otp_pgm_exit(void)
>> +{
>> + EMEMORYOTP_REG(EMEMORYOTP_PWE) = 0;
>> + clkutils_delay_ns(EMEMORYOTP_TYP_TPPH * 1000);
>> + EMEMORYOTP_REG(EMEMORYOTP_PPROG) = 0;
>> + clkutils_delay_ns(EMEMORYOTP_TYP_TPPR * 1000);
>> + EMEMORYOTP_REG(EMEMORYOTP_PCE) = 0;
>> + clkutils_delay_ns(EMEMORYOTP_MIN_TMH * 1000);
>> + EMEMORYOTP_REG(EMEMORYOTP_PTM) = 0;
>> +}
>> +
>> +void ememory_otp_pgm_access(int address, unsigned int write_data)
>> +{
>> + int i;
>> +
>> + EMEMORYOTP_REG(EMEMORYOTP_PA) = address;
>> + for (int pas = 0; pas < 2; pas++) {
>> + EMEMORYOTP_REG(EMEMORYOTP_PAS) = pas;
>> + for (i = 0; i < 32; i++) {
>> + EMEMORYOTP_REG(EMEMORYOTP_PAIO) = i;
>> + EMEMORYOTP_REG(EMEMORYOTP_PDIN) = ((write_data >> i)
>&
>> + 1);
>> +
>> + int delay = max(EMEMORYOTP_MIN_TASP,
>> + EMEMORYOTP_MIN_TDSP);
>> +
>> + clkutils_delay_ns(delay * 1000);
>> + EMEMORYOTP_REG(EMEMORYOTP_PWE) = 1;
>> + clkutils_delay_ns(EMEMORYOTP_TYP_TPW * 1000);
>> + EMEMORYOTP_REG(EMEMORYOTP_PWE) = 0;
>> + delay = max(EMEMORYOTP_MIN_TAHP,
>EMEMORYOTP_MIN_TDHP);
>> + delay = max(delay, EMEMORYOTP_TYP_TPWI);
>> + clkutils_delay_ns(delay * 1000);
>> + }
>> + }
>> + EMEMORYOTP_REG(EMEMORYOTP_PAS) = 0;
>> +}
>
>Please add dm driver for this.
I will add dm driver in v2.
>
>> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
>> index 47a2090251..e91418a88a 100644
>> --- a/board/sifive/fu540/fu540.c
>> +++ b/board/sifive/fu540/fu540.c
>> @@ -10,6 +10,9 @@
>> #include <dm.h>
>> #include <linux/delay.h>
>> #include <linux/io.h>
>> +#include <spl.h>
>> +#include "include/ccache.h"
>> +#include "include/fu540-memory-map.h"
>>
>> #ifdef CONFIG_MISC_INIT_R
>>
>> @@ -143,7 +146,33 @@ int misc_init_r(void)
>>
>> int board_init(void)
>> {
>> - /* For now nothing to do here. */
>> + /* enable all cache ways */
>> + ccache_enable_ways(CCACHE_CTRL_ADDR, 15);
>> + return 0;
>> +}
>> +
>> +#ifdef CONFIG_SPL
>> +void board_boot_order(u32 *spl_boot_list)
>> +{
>> + u8 i;
>> + u32 boot_devices[] = {
>> +#ifdef CONFIG_SPL_RAM_SUPPORT
>> + BOOT_DEVICE_RAM,
>> +#endif
>
>You may skip if you haven't tested Boot from RAM yet?
I have tested the BOOT from RAM.
>
>> +#ifdef CONFIG_SPL_MMC_SUPPORT
>> + BOOT_DEVICE_MMC1,
>> +#endif
>> + };
>>
>> + for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
>> + spl_boot_list[i] = boot_devices[i];
>> +}
>> +#endif
>> +
>> +#ifdef CONFIG_SPL_LOAD_FIT
>> +int board_fit_config_name_match(const char *name)
>> +{
>> + /* boot using first FIT config */
>> return 0;
>> }
>> +#endif
>> diff --git a/board/sifive/fu540/include/ccache.h
>b/board/sifive/fu540/include/ccache.h
>> new file mode 100644
>> index 0000000000..c7978ebdee
>> --- /dev/null
>> +++ b/board/sifive/fu540/include/ccache.h
>> @@ -0,0 +1,47 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (c) 2019 SiFive, Inc
>> + *
>> + * Authors:
>> + * Pragnesh Patel <pragnesh.patel at sifive.com>
>> + * Troy Benjegerdes <troy.benjegerdes at sifive.com>
>> + */
>> +
>> +#ifndef FU540_CCACHE_H
>> +#define FU540_CCACHE_H
>> +
>> +#include <asm/arch/cache.h>
>> +
>> +#ifndef __ASSEMBLER__
>> +
>> +#include <stdint.h>
>> +#include <stdatomic.h>
>> +#include <linux/types.h>
>> +
>> +// Block memory access until operation completed
>> +static inline void ccache_barrier_0(void)
>> +{
>> + asm volatile("fence rw, io" : : : "memory");
>> +}
>> +
>> +static inline void ccache_barrier_1(void)
>> +{
>> + asm volatile("fence io, rw" : : : "memory");
>> +}
>> +
>> +// Enable ways; allow cache to use these ways
>> +static inline u8 ccache_enable_ways(u64 base_addr, u8 value)
>> +{
>> + u32 old;
>> +
>> + volatile _Atomic(u32) * enable = (_Atomic(u32) *)(base_addr +
>> + CCACHE_ENABLE);
>> + ccache_barrier_0();
>> + old = atomic_exchange_explicit(enable, value,
>memory_order_relaxed);
>> + ccache_barrier_1();
>> + return old;
>> +}
>> +
>> +#endif
>> +
>> +#endif /* FU540_CCACHE_H */
>> diff --git a/board/sifive/fu540/include/clkutils.h
>b/board/sifive/fu540/include/clkutils.h
>> new file mode 100644
>> index 0000000000..dbb260a1c3
>> --- /dev/null
>> +++ b/board/sifive/fu540/include/clkutils.h
>> @@ -0,0 +1,75 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (c) 2019 SiFive, Inc
>> + *
>> + * Authors:
>> + * Pragnesh Patel <pragnesh.patel at sifive.com>
>> + * Troy Benjegerdes <troy.benjegerdes at sifive.com>
>> + */
>> +
>> +#ifndef __ASSEMBLER__
>> +
>> +#include <stdint.h>
>> +#include <asm/encoding.h>
>> +#include "fu540-memory-map.h"
>> +
>> +// Inlining header functions in C
>> +// https://stackoverflow.com/a/23699777/7433423
>> +inline u64 clkutils_read_mtime(void)
>> +{
>> +#if __riscv_xlen == 32
>> + u32 mtime_hi_0;
>> + u32 mtime_lo;
>> + u32 mtime_hi_1;
>> +
>> + do {
>> + mtime_hi_0 = CLINT_REG(CLINT_MTIME + 4);
>> + mtime_lo = CLINT_REG(CLINT_MTIME + 0);
>> + mtime_hi_1 = CLINT_REG(CLINT_MTIME + 4);
>> + } while (mtime_hi_0 != mtime_hi_1);
>> +
>> + return (((u64)mtime_hi_1 << 32) | ((u64)mtime_lo));
>> +#else
>> + return CLINT_REG64(CLINT_MTIME);
>> +#endif
>> +}
>> +
>> +static inline u64 clkutils_read_mcycle(void)
>> +{
>> +#if __riscv_xlen == 32
>> + u32 mcycle_hi_0;
>> + u32 mcycle_lo;
>> + u32 mcycle_hi_1;
>> +
>> + do {
>> + mcycle_hi_0 = read_csr(mcycleh);
>> + mcycle_lo = read_csr(mcycle);
>> + mcycle_hi_1 = read_csr(mcycleh);
>> + } while (mcycle_hi_0 != mcycle_hi_1);
>> +
>> + return (((u64)mcycle_hi_1 << 32) | ((u64)mcycle_lo));
>> +#else
>> + return csr_read(CSR_MCYCLE);
>> +#endif
>> +}
>> +
>> +// Note that since this runs off RTC, which is
>> +// currently ~1-10MHz, this function is
>> +// not acccurate for small delays.
>> +// In the future, we may want to determine whether to
>> +// use RTC vs mcycle, or create a different function
>> +// based off mcycle.
>> +// We add 1 to the then value because otherwise, if you wanted
>> +// to delay up to RTC_PERIOD_NS-1 (for example), you wouldn't delay
>> +// at all. So this function delays AT LEAST delay_ns.
>
>Improper syntax for multiple comments.
I will update this in v2.
>
>> +inline void clkutils_delay_ns(int delay_ns)
>> +{
>> + u64 now = clkutils_read_mtime();
>> + u64 then = now + delay_ns / RTC_PERIOD_NS + 1;
>> +
>> + do {
>> + now = clkutils_read_mtime();
>> + } while (now < then);
>> +}
>> +
>> +#endif /* !__ASSEMBLER__ */
>> diff --git a/board/sifive/fu540/include/ddrregs.h
>b/board/sifive/fu540/include/ddrregs.h
>> new file mode 100644
>> index 0000000000..e436496d87
>> --- /dev/null
>> +++ b/board/sifive/fu540/include/ddrregs.h
>> @@ -0,0 +1,622 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (c) 2019 SiFive, Inc
>> + *
>> + * Authors:
>> + * Pragnesh Patel <pragnesh.patel at sifive.com>
>> + * Troy Benjegerdes <troy.benjegerdes at sifive.com>
>> + */
>> +
>> +#include <stdint.h>
>> +
>> +u32 DENALI_PHY_DATA[1215] = {
>> + DENALI_PHY_00_DATA, DENALI_PHY_01_DATA,
>DENALI_PHY_02_DATA,
>> + DENALI_PHY_03_DATA, DENALI_PHY_04_DATA,
>DENALI_PHY_05_DATA,
>> + DENALI_PHY_06_DATA, DENALI_PHY_07_DATA,
>DENALI_PHY_08_DATA,
>> + DENALI_PHY_09_DATA,
>> + DENALI_PHY_10_DATA, DENALI_PHY_11_DATA,
>DENALI_PHY_12_DATA,
>> + DENALI_PHY_13_DATA, DENALI_PHY_14_DATA,
>DENALI_PHY_15_DATA,
>> + DENALI_PHY_16_DATA, DENALI_PHY_17_DATA,
>DENALI_PHY_18_DATA,
>> + DENALI_PHY_19_DATA,
>> + DENALI_PHY_20_DATA, DENALI_PHY_21_DATA,
>DENALI_PHY_22_DATA,
>> + DENALI_PHY_23_DATA, DENALI_PHY_24_DATA,
>DENALI_PHY_25_DATA,
>> + DENALI_PHY_26_DATA, DENALI_PHY_27_DATA,
>DENALI_PHY_28_DATA,
>> + DENALI_PHY_29_DATA,
>> + DENALI_PHY_30_DATA, DENALI_PHY_31_DATA,
>DENALI_PHY_32_DATA,
>> + DENALI_PHY_33_DATA, DENALI_PHY_34_DATA,
>DENALI_PHY_35_DATA,
>> + DENALI_PHY_36_DATA, DENALI_PHY_37_DATA,
>DENALI_PHY_38_DATA,
>> + DENALI_PHY_39_DATA,
>> + DENALI_PHY_40_DATA, DENALI_PHY_41_DATA,
>DENALI_PHY_42_DATA,
>> + DENALI_PHY_43_DATA, DENALI_PHY_44_DATA,
>DENALI_PHY_45_DATA,
>> + DENALI_PHY_46_DATA, DENALI_PHY_47_DATA,
>DENALI_PHY_48_DATA,
>> + DENALI_PHY_49_DATA,
>> + DENALI_PHY_50_DATA, DENALI_PHY_51_DATA,
>DENALI_PHY_52_DATA,
>> + DENALI_PHY_53_DATA, DENALI_PHY_54_DATA,
>DENALI_PHY_55_DATA,
>> + DENALI_PHY_56_DATA, DENALI_PHY_57_DATA,
>DENALI_PHY_58_DATA,
>> + DENALI_PHY_59_DATA,
>> + DENALI_PHY_60_DATA, DENALI_PHY_61_DATA,
>DENALI_PHY_62_DATA,
>> + DENALI_PHY_63_DATA, DENALI_PHY_64_DATA,
>DENALI_PHY_65_DATA,
>> + DENALI_PHY_66_DATA, DENALI_PHY_67_DATA,
>DENALI_PHY_68_DATA,
>> + DENALI_PHY_69_DATA,
>> + DENALI_PHY_70_DATA, DENALI_PHY_71_DATA,
>DENALI_PHY_72_DATA,
>> + DENALI_PHY_73_DATA, DENALI_PHY_74_DATA,
>DENALI_PHY_75_DATA,
>> + DENALI_PHY_76_DATA, DENALI_PHY_77_DATA,
>DENALI_PHY_78_DATA,
>> + DENALI_PHY_79_DATA,
>> + DENALI_PHY_80_DATA, DENALI_PHY_81_DATA,
>DENALI_PHY_82_DATA,
>> + DENALI_PHY_83_DATA, DENALI_PHY_84_DATA,
>DENALI_PHY_85_DATA,
>> + DENALI_PHY_86_DATA, DENALI_PHY_87_DATA,
>DENALI_PHY_88_DATA,
>> + DENALI_PHY_89_DATA,
>> + DENALI_PHY_90_DATA, DENALI_PHY_91_DATA,
>DENALI_PHY_92_DATA,
>> + DENALI_PHY_93_DATA, DENALI_PHY_94_DATA,
>DENALI_PHY_95_DATA,
>> + DENALI_PHY_96_DATA, DENALI_PHY_97_DATA,
>DENALI_PHY_98_DATA,
>> + DENALI_PHY_99_DATA,
>> +
>> + DENALI_PHY_100_DATA, DENALI_PHY_101_DATA,
>DENALI_PHY_102_DATA,
>> + DENALI_PHY_103_DATA, DENALI_PHY_104_DATA,
>DENALI_PHY_105_DATA,
>> + DENALI_PHY_106_DATA, DENALI_PHY_107_DATA,
>DENALI_PHY_108_DATA,
>> + DENALI_PHY_109_DATA,
>> + DENALI_PHY_110_DATA, DENALI_PHY_111_DATA,
>DENALI_PHY_112_DATA,
>> + DENALI_PHY_113_DATA, DENALI_PHY_114_DATA,
>DENALI_PHY_115_DATA,
>> + DENALI_PHY_116_DATA, DENALI_PHY_117_DATA,
>DENALI_PHY_118_DATA,
>> + DENALI_PHY_119_DATA,
>> + DENALI_PHY_120_DATA, DENALI_PHY_121_DATA,
>DENALI_PHY_122_DATA,
>> + DENALI_PHY_123_DATA, DENALI_PHY_124_DATA,
>DENALI_PHY_125_DATA,
>> + DENALI_PHY_126_DATA, DENALI_PHY_127_DATA,
>DENALI_PHY_128_DATA,
>> + DENALI_PHY_129_DATA,
>> + DENALI_PHY_130_DATA, DENALI_PHY_131_DATA,
>DENALI_PHY_132_DATA,
>> + DENALI_PHY_133_DATA, DENALI_PHY_134_DATA,
>DENALI_PHY_135_DATA,
>> + DENALI_PHY_136_DATA, DENALI_PHY_137_DATA,
>DENALI_PHY_138_DATA,
>> + DENALI_PHY_139_DATA,
>> + DENALI_PHY_140_DATA, DENALI_PHY_141_DATA,
>DENALI_PHY_142_DATA,
>> + DENALI_PHY_143_DATA, DENALI_PHY_144_DATA,
>DENALI_PHY_145_DATA,
>> + DENALI_PHY_146_DATA, DENALI_PHY_147_DATA,
>DENALI_PHY_148_DATA,
>> + DENALI_PHY_149_DATA,
>> + DENALI_PHY_150_DATA, DENALI_PHY_151_DATA,
>DENALI_PHY_152_DATA,
>> + DENALI_PHY_153_DATA, DENALI_PHY_154_DATA,
>DENALI_PHY_155_DATA,
>> + DENALI_PHY_156_DATA, DENALI_PHY_157_DATA,
>DENALI_PHY_158_DATA,
>> + DENALI_PHY_159_DATA,
>> + DENALI_PHY_160_DATA, DENALI_PHY_161_DATA,
>DENALI_PHY_162_DATA,
>> + DENALI_PHY_163_DATA, DENALI_PHY_164_DATA,
>DENALI_PHY_165_DATA,
>> + DENALI_PHY_166_DATA, DENALI_PHY_167_DATA,
>DENALI_PHY_168_DATA,
>> + DENALI_PHY_169_DATA,
>> + DENALI_PHY_170_DATA, DENALI_PHY_171_DATA,
>DENALI_PHY_172_DATA,
>> + DENALI_PHY_173_DATA, DENALI_PHY_174_DATA,
>DENALI_PHY_175_DATA,
>> + DENALI_PHY_176_DATA, DENALI_PHY_177_DATA,
>DENALI_PHY_178_DATA,
>> + DENALI_PHY_179_DATA,
>> + DENALI_PHY_180_DATA, DENALI_PHY_181_DATA,
>DENALI_PHY_182_DATA,
>> + DENALI_PHY_183_DATA, DENALI_PHY_184_DATA,
>DENALI_PHY_185_DATA,
>> + DENALI_PHY_186_DATA, DENALI_PHY_187_DATA,
>DENALI_PHY_188_DATA,
>> + DENALI_PHY_189_DATA,
>> + DENALI_PHY_190_DATA, DENALI_PHY_191_DATA,
>DENALI_PHY_192_DATA,
>> + DENALI_PHY_193_DATA, DENALI_PHY_194_DATA,
>DENALI_PHY_195_DATA,
>> + DENALI_PHY_196_DATA, DENALI_PHY_197_DATA,
>DENALI_PHY_198_DATA,
>> + DENALI_PHY_199_DATA,
>> +
>> + DENALI_PHY_200_DATA, DENALI_PHY_201_DATA,
>DENALI_PHY_202_DATA,
>> + DENALI_PHY_203_DATA, DENALI_PHY_204_DATA,
>DENALI_PHY_205_DATA,
>> + DENALI_PHY_206_DATA, DENALI_PHY_207_DATA,
>DENALI_PHY_208_DATA,
>> + DENALI_PHY_209_DATA,
>> + DENALI_PHY_210_DATA, DENALI_PHY_211_DATA,
>DENALI_PHY_212_DATA,
>> + DENALI_PHY_213_DATA, DENALI_PHY_214_DATA,
>DENALI_PHY_215_DATA,
>> + DENALI_PHY_216_DATA, DENALI_PHY_217_DATA,
>DENALI_PHY_218_DATA,
>> + DENALI_PHY_219_DATA,
>> + DENALI_PHY_220_DATA, DENALI_PHY_221_DATA,
>DENALI_PHY_222_DATA,
>> + DENALI_PHY_223_DATA, DENALI_PHY_224_DATA,
>DENALI_PHY_225_DATA,
>> + DENALI_PHY_226_DATA, DENALI_PHY_227_DATA,
>DENALI_PHY_228_DATA,
>> + DENALI_PHY_229_DATA,
>> + DENALI_PHY_230_DATA, DENALI_PHY_231_DATA,
>DENALI_PHY_232_DATA,
>> + DENALI_PHY_233_DATA, DENALI_PHY_234_DATA,
>DENALI_PHY_235_DATA,
>> + DENALI_PHY_236_DATA, DENALI_PHY_237_DATA,
>DENALI_PHY_238_DATA,
>> + DENALI_PHY_239_DATA,
>> + DENALI_PHY_240_DATA, DENALI_PHY_241_DATA,
>DENALI_PHY_242_DATA,
>> + DENALI_PHY_243_DATA, DENALI_PHY_244_DATA,
>DENALI_PHY_245_DATA,
>> + DENALI_PHY_246_DATA, DENALI_PHY_247_DATA,
>DENALI_PHY_248_DATA,
>> + DENALI_PHY_249_DATA,
>> + DENALI_PHY_250_DATA, DENALI_PHY_251_DATA,
>DENALI_PHY_252_DATA,
>> + DENALI_PHY_253_DATA, DENALI_PHY_254_DATA,
>DENALI_PHY_255_DATA,
>> + DENALI_PHY_256_DATA, DENALI_PHY_257_DATA,
>DENALI_PHY_258_DATA,
>> + DENALI_PHY_259_DATA,
>> + DENALI_PHY_260_DATA, DENALI_PHY_261_DATA,
>DENALI_PHY_262_DATA,
>> + DENALI_PHY_263_DATA, DENALI_PHY_264_DATA,
>DENALI_PHY_265_DATA,
>> + DENALI_PHY_266_DATA, DENALI_PHY_267_DATA,
>DENALI_PHY_268_DATA,
>> + DENALI_PHY_269_DATA,
>> + DENALI_PHY_270_DATA, DENALI_PHY_271_DATA,
>DENALI_PHY_272_DATA,
>> + DENALI_PHY_273_DATA, DENALI_PHY_274_DATA,
>DENALI_PHY_275_DATA,
>> + DENALI_PHY_276_DATA, DENALI_PHY_277_DATA,
>DENALI_PHY_278_DATA,
>> + DENALI_PHY_279_DATA,
>> + DENALI_PHY_280_DATA, DENALI_PHY_281_DATA,
>DENALI_PHY_282_DATA,
>> + DENALI_PHY_283_DATA, DENALI_PHY_284_DATA,
>DENALI_PHY_285_DATA,
>> + DENALI_PHY_286_DATA, DENALI_PHY_287_DATA,
>DENALI_PHY_288_DATA,
>> + DENALI_PHY_289_DATA,
>> + DENALI_PHY_290_DATA, DENALI_PHY_291_DATA,
>DENALI_PHY_292_DATA,
>> + DENALI_PHY_293_DATA, DENALI_PHY_294_DATA,
>DENALI_PHY_295_DATA,
>> + DENALI_PHY_296_DATA, DENALI_PHY_297_DATA,
>DENALI_PHY_298_DATA,
>> + DENALI_PHY_299_DATA,
>> +
>> + DENALI_PHY_300_DATA, DENALI_PHY_301_DATA,
>DENALI_PHY_302_DATA,
>> + DENALI_PHY_303_DATA, DENALI_PHY_304_DATA,
>DENALI_PHY_305_DATA,
>> + DENALI_PHY_306_DATA, DENALI_PHY_307_DATA,
>DENALI_PHY_308_DATA,
>> + DENALI_PHY_309_DATA,
>> + DENALI_PHY_310_DATA, DENALI_PHY_311_DATA,
>DENALI_PHY_312_DATA,
>> + DENALI_PHY_313_DATA, DENALI_PHY_314_DATA,
>DENALI_PHY_315_DATA,
>> + DENALI_PHY_316_DATA, DENALI_PHY_317_DATA,
>DENALI_PHY_318_DATA,
>> + DENALI_PHY_319_DATA,
>> + DENALI_PHY_320_DATA, DENALI_PHY_321_DATA,
>DENALI_PHY_322_DATA,
>> + DENALI_PHY_323_DATA, DENALI_PHY_324_DATA,
>DENALI_PHY_325_DATA,
>> + DENALI_PHY_326_DATA, DENALI_PHY_327_DATA,
>DENALI_PHY_328_DATA,
>> + DENALI_PHY_329_DATA,
>> + DENALI_PHY_330_DATA, DENALI_PHY_331_DATA,
>DENALI_PHY_332_DATA,
>> + DENALI_PHY_333_DATA, DENALI_PHY_334_DATA,
>DENALI_PHY_335_DATA,
>> + DENALI_PHY_336_DATA, DENALI_PHY_337_DATA,
>DENALI_PHY_338_DATA,
>> + DENALI_PHY_339_DATA,
>> + DENALI_PHY_340_DATA, DENALI_PHY_341_DATA,
>DENALI_PHY_342_DATA,
>> + DENALI_PHY_343_DATA, DENALI_PHY_344_DATA,
>DENALI_PHY_345_DATA,
>> + DENALI_PHY_346_DATA, DENALI_PHY_347_DATA,
>DENALI_PHY_348_DATA,
>> + DENALI_PHY_349_DATA,
>> + DENALI_PHY_350_DATA, DENALI_PHY_351_DATA,
>DENALI_PHY_352_DATA,
>> + DENALI_PHY_353_DATA, DENALI_PHY_354_DATA,
>DENALI_PHY_355_DATA,
>> + DENALI_PHY_356_DATA, DENALI_PHY_357_DATA,
>DENALI_PHY_358_DATA,
>> + DENALI_PHY_359_DATA,
>> + DENALI_PHY_360_DATA, DENALI_PHY_361_DATA,
>DENALI_PHY_362_DATA,
>> + DENALI_PHY_363_DATA, DENALI_PHY_364_DATA,
>DENALI_PHY_365_DATA,
>> + DENALI_PHY_366_DATA, DENALI_PHY_367_DATA,
>DENALI_PHY_368_DATA,
>> + DENALI_PHY_369_DATA,
>> + DENALI_PHY_370_DATA, DENALI_PHY_371_DATA,
>DENALI_PHY_372_DATA,
>> + DENALI_PHY_373_DATA, DENALI_PHY_374_DATA,
>DENALI_PHY_375_DATA,
>> + DENALI_PHY_376_DATA, DENALI_PHY_377_DATA,
>DENALI_PHY_378_DATA,
>> + DENALI_PHY_379_DATA,
>> + DENALI_PHY_380_DATA, DENALI_PHY_381_DATA,
>DENALI_PHY_382_DATA,
>> + DENALI_PHY_383_DATA, DENALI_PHY_384_DATA,
>DENALI_PHY_385_DATA,
>> + DENALI_PHY_386_DATA, DENALI_PHY_387_DATA,
>DENALI_PHY_388_DATA,
>> + DENALI_PHY_389_DATA,
>> + DENALI_PHY_390_DATA, DENALI_PHY_391_DATA,
>DENALI_PHY_392_DATA,
>> + DENALI_PHY_393_DATA, DENALI_PHY_394_DATA,
>DENALI_PHY_395_DATA,
>> + DENALI_PHY_396_DATA, DENALI_PHY_397_DATA,
>DENALI_PHY_398_DATA,
>> + DENALI_PHY_399_DATA,
>> +
>> + DENALI_PHY_400_DATA, DENALI_PHY_401_DATA,
>DENALI_PHY_402_DATA,
>> + DENALI_PHY_403_DATA, DENALI_PHY_404_DATA,
>DENALI_PHY_405_DATA,
>> + DENALI_PHY_406_DATA, DENALI_PHY_407_DATA,
>DENALI_PHY_408_DATA,
>> + DENALI_PHY_409_DATA,
>> + DENALI_PHY_410_DATA, DENALI_PHY_411_DATA,
>DENALI_PHY_412_DATA,
>> + DENALI_PHY_413_DATA, DENALI_PHY_414_DATA,
>DENALI_PHY_415_DATA,
>> + DENALI_PHY_416_DATA, DENALI_PHY_417_DATA,
>DENALI_PHY_418_DATA,
>> + DENALI_PHY_419_DATA,
>> + DENALI_PHY_420_DATA, DENALI_PHY_421_DATA,
>DENALI_PHY_422_DATA,
>> + DENALI_PHY_423_DATA, DENALI_PHY_424_DATA,
>DENALI_PHY_425_DATA,
>> + DENALI_PHY_426_DATA, DENALI_PHY_427_DATA,
>DENALI_PHY_428_DATA,
>> + DENALI_PHY_429_DATA,
>> + DENALI_PHY_430_DATA, DENALI_PHY_431_DATA,
>DENALI_PHY_432_DATA,
>> + DENALI_PHY_433_DATA, DENALI_PHY_434_DATA,
>DENALI_PHY_435_DATA,
>> + DENALI_PHY_436_DATA, DENALI_PHY_437_DATA,
>DENALI_PHY_438_DATA,
>> + DENALI_PHY_439_DATA,
>> + DENALI_PHY_440_DATA, DENALI_PHY_441_DATA,
>DENALI_PHY_442_DATA,
>> + DENALI_PHY_443_DATA, DENALI_PHY_444_DATA,
>DENALI_PHY_445_DATA,
>> + DENALI_PHY_446_DATA, DENALI_PHY_447_DATA,
>DENALI_PHY_448_DATA,
>> + DENALI_PHY_449_DATA,
>> + DENALI_PHY_450_DATA, DENALI_PHY_451_DATA,
>DENALI_PHY_452_DATA,
>> + DENALI_PHY_453_DATA, DENALI_PHY_454_DATA,
>DENALI_PHY_455_DATA,
>> + DENALI_PHY_456_DATA, DENALI_PHY_457_DATA,
>DENALI_PHY_458_DATA,
>> + DENALI_PHY_459_DATA,
>> + DENALI_PHY_460_DATA, DENALI_PHY_461_DATA,
>DENALI_PHY_462_DATA,
>> + DENALI_PHY_463_DATA, DENALI_PHY_464_DATA,
>DENALI_PHY_465_DATA,
>> + DENALI_PHY_466_DATA, DENALI_PHY_467_DATA,
>DENALI_PHY_468_DATA,
>> + DENALI_PHY_469_DATA,
>> + DENALI_PHY_470_DATA, DENALI_PHY_471_DATA,
>DENALI_PHY_472_DATA,
>> + DENALI_PHY_473_DATA, DENALI_PHY_474_DATA,
>DENALI_PHY_475_DATA,
>> + DENALI_PHY_476_DATA, DENALI_PHY_477_DATA,
>DENALI_PHY_478_DATA,
>> + DENALI_PHY_479_DATA,
>> + DENALI_PHY_480_DATA, DENALI_PHY_481_DATA,
>DENALI_PHY_482_DATA,
>> + DENALI_PHY_483_DATA, DENALI_PHY_484_DATA,
>DENALI_PHY_485_DATA,
>> + DENALI_PHY_486_DATA, DENALI_PHY_487_DATA,
>DENALI_PHY_488_DATA,
>> + DENALI_PHY_489_DATA,
>> + DENALI_PHY_490_DATA, DENALI_PHY_491_DATA,
>DENALI_PHY_492_DATA,
>> + DENALI_PHY_493_DATA, DENALI_PHY_494_DATA,
>DENALI_PHY_495_DATA,
>> + DENALI_PHY_496_DATA, DENALI_PHY_497_DATA,
>DENALI_PHY_498_DATA,
>> + DENALI_PHY_499_DATA,
>> +
>> + DENALI_PHY_500_DATA, DENALI_PHY_501_DATA,
>DENALI_PHY_502_DATA,
>> + DENALI_PHY_503_DATA, DENALI_PHY_504_DATA,
>DENALI_PHY_505_DATA,
>> + DENALI_PHY_506_DATA, DENALI_PHY_507_DATA,
>DENALI_PHY_508_DATA,
>> + DENALI_PHY_509_DATA,
>> + DENALI_PHY_510_DATA, DENALI_PHY_511_DATA,
>DENALI_PHY_512_DATA,
>> + DENALI_PHY_513_DATA, DENALI_PHY_514_DATA,
>DENALI_PHY_515_DATA,
>> + DENALI_PHY_516_DATA, DENALI_PHY_517_DATA,
>DENALI_PHY_518_DATA,
>> + DENALI_PHY_519_DATA,
>> + DENALI_PHY_520_DATA, DENALI_PHY_521_DATA,
>DENALI_PHY_522_DATA,
>> + DENALI_PHY_523_DATA, DENALI_PHY_524_DATA,
>DENALI_PHY_525_DATA,
>> + DENALI_PHY_526_DATA, DENALI_PHY_527_DATA,
>DENALI_PHY_528_DATA,
>> + DENALI_PHY_529_DATA,
>> + DENALI_PHY_530_DATA, DENALI_PHY_531_DATA,
>DENALI_PHY_532_DATA,
>> + DENALI_PHY_533_DATA, DENALI_PHY_534_DATA,
>DENALI_PHY_535_DATA,
>> + DENALI_PHY_536_DATA, DENALI_PHY_537_DATA,
>DENALI_PHY_538_DATA,
>> + DENALI_PHY_539_DATA,
>> + DENALI_PHY_540_DATA, DENALI_PHY_541_DATA,
>DENALI_PHY_542_DATA,
>> + DENALI_PHY_543_DATA, DENALI_PHY_544_DATA,
>DENALI_PHY_545_DATA,
>> + DENALI_PHY_546_DATA, DENALI_PHY_547_DATA,
>DENALI_PHY_548_DATA,
>> + DENALI_PHY_549_DATA,
>> + DENALI_PHY_550_DATA, DENALI_PHY_551_DATA,
>DENALI_PHY_552_DATA,
>> + DENALI_PHY_553_DATA, DENALI_PHY_554_DATA,
>DENALI_PHY_555_DATA,
>> + DENALI_PHY_556_DATA, DENALI_PHY_557_DATA,
>DENALI_PHY_558_DATA,
>> + DENALI_PHY_559_DATA,
>> + DENALI_PHY_560_DATA, DENALI_PHY_561_DATA,
>DENALI_PHY_562_DATA,
>> + DENALI_PHY_563_DATA, DENALI_PHY_564_DATA,
>DENALI_PHY_565_DATA,
>> + DENALI_PHY_566_DATA, DENALI_PHY_567_DATA,
>DENALI_PHY_568_DATA,
>> + DENALI_PHY_569_DATA,
>> + DENALI_PHY_570_DATA, DENALI_PHY_571_DATA,
>DENALI_PHY_572_DATA,
>> + DENALI_PHY_573_DATA, DENALI_PHY_574_DATA,
>DENALI_PHY_575_DATA,
>> + DENALI_PHY_576_DATA, DENALI_PHY_577_DATA,
>DENALI_PHY_578_DATA,
>> + DENALI_PHY_579_DATA,
>> + DENALI_PHY_580_DATA, DENALI_PHY_581_DATA,
>DENALI_PHY_582_DATA,
>> + DENALI_PHY_583_DATA, DENALI_PHY_584_DATA,
>DENALI_PHY_585_DATA,
>> + DENALI_PHY_586_DATA, DENALI_PHY_587_DATA,
>DENALI_PHY_588_DATA,
>> + DENALI_PHY_589_DATA,
>> + DENALI_PHY_590_DATA, DENALI_PHY_591_DATA,
>DENALI_PHY_592_DATA,
>> + DENALI_PHY_593_DATA, DENALI_PHY_594_DATA,
>DENALI_PHY_595_DATA,
>> + DENALI_PHY_596_DATA, DENALI_PHY_597_DATA,
>DENALI_PHY_598_DATA,
>> + DENALI_PHY_599_DATA,
>> +
>> + DENALI_PHY_600_DATA, DENALI_PHY_601_DATA,
>DENALI_PHY_602_DATA,
>> + DENALI_PHY_603_DATA, DENALI_PHY_604_DATA,
>DENALI_PHY_605_DATA,
>> + DENALI_PHY_606_DATA, DENALI_PHY_607_DATA,
>DENALI_PHY_608_DATA,
>> + DENALI_PHY_609_DATA,
>> + DENALI_PHY_610_DATA, DENALI_PHY_611_DATA,
>DENALI_PHY_612_DATA,
>> + DENALI_PHY_613_DATA, DENALI_PHY_614_DATA,
>DENALI_PHY_615_DATA,
>> + DENALI_PHY_616_DATA, DENALI_PHY_617_DATA,
>DENALI_PHY_618_DATA,
>> + DENALI_PHY_619_DATA,
>> + DENALI_PHY_620_DATA, DENALI_PHY_621_DATA,
>DENALI_PHY_622_DATA,
>> + DENALI_PHY_623_DATA, DENALI_PHY_624_DATA,
>DENALI_PHY_625_DATA,
>> + DENALI_PHY_626_DATA, DENALI_PHY_627_DATA,
>DENALI_PHY_628_DATA,
>> + DENALI_PHY_629_DATA,
>> + DENALI_PHY_630_DATA, DENALI_PHY_631_DATA,
>DENALI_PHY_632_DATA,
>> + DENALI_PHY_633_DATA, DENALI_PHY_634_DATA,
>DENALI_PHY_635_DATA,
>> + DENALI_PHY_636_DATA, DENALI_PHY_637_DATA,
>DENALI_PHY_638_DATA,
>> + DENALI_PHY_639_DATA,
>> + DENALI_PHY_640_DATA, DENALI_PHY_641_DATA,
>DENALI_PHY_642_DATA,
>> + DENALI_PHY_643_DATA, DENALI_PHY_644_DATA,
>DENALI_PHY_645_DATA,
>> + DENALI_PHY_646_DATA, DENALI_PHY_647_DATA,
>DENALI_PHY_648_DATA,
>> + DENALI_PHY_649_DATA,
>> + DENALI_PHY_650_DATA, DENALI_PHY_651_DATA,
>DENALI_PHY_652_DATA,
>> + DENALI_PHY_653_DATA, DENALI_PHY_654_DATA,
>DENALI_PHY_655_DATA,
>> + DENALI_PHY_656_DATA, DENALI_PHY_657_DATA,
>DENALI_PHY_658_DATA,
>> + DENALI_PHY_659_DATA,
>> + DENALI_PHY_660_DATA, DENALI_PHY_661_DATA,
>DENALI_PHY_662_DATA,
>> + DENALI_PHY_663_DATA, DENALI_PHY_664_DATA,
>DENALI_PHY_665_DATA,
>> + DENALI_PHY_666_DATA, DENALI_PHY_667_DATA,
>DENALI_PHY_668_DATA,
>> + DENALI_PHY_669_DATA,
>> + DENALI_PHY_670_DATA, DENALI_PHY_671_DATA,
>DENALI_PHY_672_DATA,
>> + DENALI_PHY_673_DATA, DENALI_PHY_674_DATA,
>DENALI_PHY_675_DATA,
>> + DENALI_PHY_676_DATA, DENALI_PHY_677_DATA,
>DENALI_PHY_678_DATA,
>> + DENALI_PHY_679_DATA,
>> + DENALI_PHY_680_DATA, DENALI_PHY_681_DATA,
>DENALI_PHY_682_DATA,
>> + DENALI_PHY_683_DATA, DENALI_PHY_684_DATA,
>DENALI_PHY_685_DATA,
>> + DENALI_PHY_686_DATA, DENALI_PHY_687_DATA,
>DENALI_PHY_688_DATA,
>> + DENALI_PHY_689_DATA,
>> + DENALI_PHY_690_DATA, DENALI_PHY_691_DATA,
>DENALI_PHY_692_DATA,
>> + DENALI_PHY_693_DATA, DENALI_PHY_694_DATA,
>DENALI_PHY_695_DATA,
>> + DENALI_PHY_696_DATA, DENALI_PHY_697_DATA,
>DENALI_PHY_698_DATA,
>> + DENALI_PHY_699_DATA,
>> +
>> + DENALI_PHY_700_DATA, DENALI_PHY_701_DATA,
>DENALI_PHY_702_DATA,
>> + DENALI_PHY_703_DATA, DENALI_PHY_704_DATA,
>DENALI_PHY_705_DATA,
>> + DENALI_PHY_706_DATA, DENALI_PHY_707_DATA,
>DENALI_PHY_708_DATA,
>> + DENALI_PHY_709_DATA,
>> + DENALI_PHY_710_DATA, DENALI_PHY_711_DATA,
>DENALI_PHY_712_DATA,
>> + DENALI_PHY_713_DATA, DENALI_PHY_714_DATA,
>DENALI_PHY_715_DATA,
>> + DENALI_PHY_716_DATA, DENALI_PHY_717_DATA,
>DENALI_PHY_718_DATA,
>> + DENALI_PHY_719_DATA,
>> + DENALI_PHY_720_DATA, DENALI_PHY_721_DATA,
>DENALI_PHY_722_DATA,
>> + DENALI_PHY_723_DATA, DENALI_PHY_724_DATA,
>DENALI_PHY_725_DATA,
>> + DENALI_PHY_726_DATA, DENALI_PHY_727_DATA,
>DENALI_PHY_728_DATA,
>> + DENALI_PHY_729_DATA,
>> + DENALI_PHY_730_DATA, DENALI_PHY_731_DATA,
>DENALI_PHY_732_DATA,
>> + DENALI_PHY_733_DATA, DENALI_PHY_734_DATA,
>DENALI_PHY_735_DATA,
>> + DENALI_PHY_736_DATA, DENALI_PHY_737_DATA,
>DENALI_PHY_738_DATA,
>> + DENALI_PHY_739_DATA,
>> + DENALI_PHY_740_DATA, DENALI_PHY_741_DATA,
>DENALI_PHY_742_DATA,
>> + DENALI_PHY_743_DATA, DENALI_PHY_744_DATA,
>DENALI_PHY_745_DATA,
>> + DENALI_PHY_746_DATA, DENALI_PHY_747_DATA,
>DENALI_PHY_748_DATA,
>> + DENALI_PHY_749_DATA,
>> + DENALI_PHY_750_DATA, DENALI_PHY_751_DATA,
>DENALI_PHY_752_DATA,
>> + DENALI_PHY_753_DATA, DENALI_PHY_754_DATA,
>DENALI_PHY_755_DATA,
>> + DENALI_PHY_756_DATA, DENALI_PHY_757_DATA,
>DENALI_PHY_758_DATA,
>> + DENALI_PHY_759_DATA,
>> + DENALI_PHY_760_DATA, DENALI_PHY_761_DATA,
>DENALI_PHY_762_DATA,
>> + DENALI_PHY_763_DATA, DENALI_PHY_764_DATA,
>DENALI_PHY_765_DATA,
>> + DENALI_PHY_766_DATA, DENALI_PHY_767_DATA,
>DENALI_PHY_768_DATA,
>> + DENALI_PHY_769_DATA,
>> + DENALI_PHY_770_DATA, DENALI_PHY_771_DATA,
>DENALI_PHY_772_DATA,
>> + DENALI_PHY_773_DATA, DENALI_PHY_774_DATA,
>DENALI_PHY_775_DATA,
>> + DENALI_PHY_776_DATA, DENALI_PHY_777_DATA,
>DENALI_PHY_778_DATA,
>> + DENALI_PHY_779_DATA,
>> + DENALI_PHY_780_DATA, DENALI_PHY_781_DATA,
>DENALI_PHY_782_DATA,
>> + DENALI_PHY_783_DATA, DENALI_PHY_784_DATA,
>DENALI_PHY_785_DATA,
>> + DENALI_PHY_786_DATA, DENALI_PHY_787_DATA,
>DENALI_PHY_788_DATA,
>> + DENALI_PHY_789_DATA,
>> + DENALI_PHY_790_DATA, DENALI_PHY_791_DATA,
>DENALI_PHY_792_DATA,
>> + DENALI_PHY_793_DATA, DENALI_PHY_794_DATA,
>DENALI_PHY_795_DATA,
>> + DENALI_PHY_796_DATA, DENALI_PHY_797_DATA,
>DENALI_PHY_798_DATA,
>> + DENALI_PHY_799_DATA,
>> +
>> + DENALI_PHY_800_DATA, DENALI_PHY_801_DATA,
>DENALI_PHY_802_DATA,
>> + DENALI_PHY_803_DATA, DENALI_PHY_804_DATA,
>DENALI_PHY_805_DATA,
>> + DENALI_PHY_806_DATA, DENALI_PHY_807_DATA,
>DENALI_PHY_808_DATA,
>> + DENALI_PHY_809_DATA,
>> + DENALI_PHY_810_DATA, DENALI_PHY_811_DATA,
>DENALI_PHY_812_DATA,
>> + DENALI_PHY_813_DATA, DENALI_PHY_814_DATA,
>DENALI_PHY_815_DATA,
>> + DENALI_PHY_816_DATA, DENALI_PHY_817_DATA,
>DENALI_PHY_818_DATA,
>> + DENALI_PHY_819_DATA,
>> + DENALI_PHY_820_DATA, DENALI_PHY_821_DATA,
>DENALI_PHY_822_DATA,
>> + DENALI_PHY_823_DATA, DENALI_PHY_824_DATA,
>DENALI_PHY_825_DATA,
>> + DENALI_PHY_826_DATA, DENALI_PHY_827_DATA,
>DENALI_PHY_828_DATA,
>> + DENALI_PHY_829_DATA,
>> + DENALI_PHY_830_DATA, DENALI_PHY_831_DATA,
>DENALI_PHY_832_DATA,
>> + DENALI_PHY_833_DATA, DENALI_PHY_834_DATA,
>DENALI_PHY_835_DATA,
>> + DENALI_PHY_836_DATA, DENALI_PHY_837_DATA,
>DENALI_PHY_838_DATA,
>> + DENALI_PHY_839_DATA,
>> + DENALI_PHY_840_DATA, DENALI_PHY_841_DATA,
>DENALI_PHY_842_DATA,
>> + DENALI_PHY_843_DATA, DENALI_PHY_844_DATA,
>DENALI_PHY_845_DATA,
>> + DENALI_PHY_846_DATA, DENALI_PHY_847_DATA,
>DENALI_PHY_848_DATA,
>> + DENALI_PHY_849_DATA,
>> + DENALI_PHY_850_DATA, DENALI_PHY_851_DATA,
>DENALI_PHY_852_DATA,
>> + DENALI_PHY_853_DATA, DENALI_PHY_854_DATA,
>DENALI_PHY_855_DATA,
>> + DENALI_PHY_856_DATA, DENALI_PHY_857_DATA,
>DENALI_PHY_858_DATA,
>> + DENALI_PHY_859_DATA,
>> + DENALI_PHY_860_DATA, DENALI_PHY_861_DATA,
>DENALI_PHY_862_DATA,
>> + DENALI_PHY_863_DATA, DENALI_PHY_864_DATA,
>DENALI_PHY_865_DATA,
>> + DENALI_PHY_866_DATA, DENALI_PHY_867_DATA,
>DENALI_PHY_868_DATA,
>> + DENALI_PHY_869_DATA,
>> + DENALI_PHY_870_DATA, DENALI_PHY_871_DATA,
>DENALI_PHY_872_DATA,
>> + DENALI_PHY_873_DATA, DENALI_PHY_874_DATA,
>DENALI_PHY_875_DATA,
>> + DENALI_PHY_876_DATA, DENALI_PHY_877_DATA,
>DENALI_PHY_878_DATA,
>> + DENALI_PHY_879_DATA,
>> + DENALI_PHY_880_DATA, DENALI_PHY_881_DATA,
>DENALI_PHY_882_DATA,
>> + DENALI_PHY_883_DATA, DENALI_PHY_884_DATA,
>DENALI_PHY_885_DATA,
>> + DENALI_PHY_886_DATA, DENALI_PHY_887_DATA,
>DENALI_PHY_888_DATA,
>> + DENALI_PHY_889_DATA,
>> + DENALI_PHY_890_DATA, DENALI_PHY_891_DATA,
>DENALI_PHY_892_DATA,
>> + DENALI_PHY_893_DATA, DENALI_PHY_894_DATA,
>DENALI_PHY_895_DATA,
>> + DENALI_PHY_896_DATA, DENALI_PHY_897_DATA,
>DENALI_PHY_898_DATA,
>> + DENALI_PHY_899_DATA,
>> +
>> + DENALI_PHY_900_DATA, DENALI_PHY_901_DATA,
>DENALI_PHY_902_DATA,
>> + DENALI_PHY_903_DATA, DENALI_PHY_904_DATA,
>DENALI_PHY_905_DATA,
>> + DENALI_PHY_906_DATA, DENALI_PHY_907_DATA,
>DENALI_PHY_908_DATA,
>> + DENALI_PHY_909_DATA,
>> + DENALI_PHY_910_DATA, DENALI_PHY_911_DATA,
>DENALI_PHY_912_DATA,
>> + DENALI_PHY_913_DATA, DENALI_PHY_914_DATA,
>DENALI_PHY_915_DATA,
>> + DENALI_PHY_916_DATA, DENALI_PHY_917_DATA,
>DENALI_PHY_918_DATA,
>> + DENALI_PHY_919_DATA,
>> + DENALI_PHY_920_DATA, DENALI_PHY_921_DATA,
>DENALI_PHY_922_DATA,
>> + DENALI_PHY_923_DATA, DENALI_PHY_924_DATA,
>DENALI_PHY_925_DATA,
>> + DENALI_PHY_926_DATA, DENALI_PHY_927_DATA,
>DENALI_PHY_928_DATA,
>> + DENALI_PHY_929_DATA,
>> + DENALI_PHY_930_DATA, DENALI_PHY_931_DATA,
>DENALI_PHY_932_DATA,
>> + DENALI_PHY_933_DATA, DENALI_PHY_934_DATA,
>DENALI_PHY_935_DATA,
>> + DENALI_PHY_936_DATA, DENALI_PHY_937_DATA,
>DENALI_PHY_938_DATA,
>> + DENALI_PHY_939_DATA,
>> + DENALI_PHY_940_DATA, DENALI_PHY_941_DATA,
>DENALI_PHY_942_DATA,
>> + DENALI_PHY_943_DATA, DENALI_PHY_944_DATA,
>DENALI_PHY_945_DATA,
>> + DENALI_PHY_946_DATA, DENALI_PHY_947_DATA,
>DENALI_PHY_948_DATA,
>> + DENALI_PHY_949_DATA,
>> + DENALI_PHY_950_DATA, DENALI_PHY_951_DATA,
>DENALI_PHY_952_DATA,
>> + DENALI_PHY_953_DATA, DENALI_PHY_954_DATA,
>DENALI_PHY_955_DATA,
>> + DENALI_PHY_956_DATA, DENALI_PHY_957_DATA,
>DENALI_PHY_958_DATA,
>> + DENALI_PHY_959_DATA,
>> + DENALI_PHY_960_DATA, DENALI_PHY_961_DATA,
>DENALI_PHY_962_DATA,
>> + DENALI_PHY_963_DATA, DENALI_PHY_964_DATA,
>DENALI_PHY_965_DATA,
>> + DENALI_PHY_966_DATA, DENALI_PHY_967_DATA,
>DENALI_PHY_968_DATA,
>> + DENALI_PHY_969_DATA,
>> + DENALI_PHY_970_DATA, DENALI_PHY_971_DATA,
>DENALI_PHY_972_DATA,
>> + DENALI_PHY_973_DATA, DENALI_PHY_974_DATA,
>DENALI_PHY_975_DATA,
>> + DENALI_PHY_976_DATA, DENALI_PHY_977_DATA,
>DENALI_PHY_978_DATA,
>> + DENALI_PHY_979_DATA,
>> + DENALI_PHY_980_DATA, DENALI_PHY_981_DATA,
>DENALI_PHY_982_DATA,
>> + DENALI_PHY_983_DATA, DENALI_PHY_984_DATA,
>DENALI_PHY_985_DATA,
>> + DENALI_PHY_986_DATA, DENALI_PHY_987_DATA,
>DENALI_PHY_988_DATA,
>> + DENALI_PHY_989_DATA,
>> + DENALI_PHY_990_DATA, DENALI_PHY_991_DATA,
>DENALI_PHY_992_DATA,
>> + DENALI_PHY_993_DATA, DENALI_PHY_994_DATA,
>DENALI_PHY_995_DATA,
>> + DENALI_PHY_996_DATA, DENALI_PHY_997_DATA,
>DENALI_PHY_998_DATA,
>> + DENALI_PHY_999_DATA,
>> +
>> + DENALI_PHY_1000_DATA, DENALI_PHY_1001_DATA,
>DENALI_PHY_1002_DATA,
>> + DENALI_PHY_1003_DATA, DENALI_PHY_1004_DATA,
>DENALI_PHY_1005_DATA,
>> + DENALI_PHY_1006_DATA, DENALI_PHY_1007_DATA,
>DENALI_PHY_1008_DATA,
>> + DENALI_PHY_1009_DATA,
>> + DENALI_PHY_1010_DATA, DENALI_PHY_1011_DATA,
>DENALI_PHY_1012_DATA,
>> + DENALI_PHY_1013_DATA, DENALI_PHY_1014_DATA,
>DENALI_PHY_1015_DATA,
>> + DENALI_PHY_1016_DATA, DENALI_PHY_1017_DATA,
>DENALI_PHY_1018_DATA,
>> + DENALI_PHY_1019_DATA,
>> + DENALI_PHY_1020_DATA, DENALI_PHY_1021_DATA,
>DENALI_PHY_1022_DATA,
>> + DENALI_PHY_1023_DATA, DENALI_PHY_1024_DATA,
>DENALI_PHY_1025_DATA,
>> + DENALI_PHY_1026_DATA, DENALI_PHY_1027_DATA,
>DENALI_PHY_1028_DATA,
>> + DENALI_PHY_1029_DATA,
>> + DENALI_PHY_1030_DATA, DENALI_PHY_1031_DATA,
>DENALI_PHY_1032_DATA,
>> + DENALI_PHY_1033_DATA, DENALI_PHY_1034_DATA,
>DENALI_PHY_1035_DATA,
>> + DENALI_PHY_1036_DATA, DENALI_PHY_1037_DATA,
>DENALI_PHY_1038_DATA,
>> + DENALI_PHY_1039_DATA,
>> + DENALI_PHY_1040_DATA, DENALI_PHY_1041_DATA,
>DENALI_PHY_1042_DATA,
>> + DENALI_PHY_1043_DATA, DENALI_PHY_1044_DATA,
>DENALI_PHY_1045_DATA,
>> + DENALI_PHY_1046_DATA, DENALI_PHY_1047_DATA,
>DENALI_PHY_1048_DATA,
>> + DENALI_PHY_1049_DATA,
>> + DENALI_PHY_1050_DATA, DENALI_PHY_1051_DATA,
>DENALI_PHY_1052_DATA,
>> + DENALI_PHY_1053_DATA, DENALI_PHY_1054_DATA,
>DENALI_PHY_1055_DATA,
>> + DENALI_PHY_1056_DATA, DENALI_PHY_1057_DATA,
>DENALI_PHY_1058_DATA,
>> + DENALI_PHY_1059_DATA,
>> + DENALI_PHY_1060_DATA, DENALI_PHY_1061_DATA,
>DENALI_PHY_1062_DATA,
>> + DENALI_PHY_1063_DATA, DENALI_PHY_1064_DATA,
>DENALI_PHY_1065_DATA,
>> + DENALI_PHY_1066_DATA, DENALI_PHY_1067_DATA,
>DENALI_PHY_1068_DATA,
>> + DENALI_PHY_1069_DATA,
>> + DENALI_PHY_1070_DATA, DENALI_PHY_1071_DATA,
>DENALI_PHY_1072_DATA,
>> + DENALI_PHY_1073_DATA, DENALI_PHY_1074_DATA,
>DENALI_PHY_1075_DATA,
>> + DENALI_PHY_1076_DATA, DENALI_PHY_1077_DATA,
>DENALI_PHY_1078_DATA,
>> + DENALI_PHY_1079_DATA,
>> + DENALI_PHY_1080_DATA, DENALI_PHY_1081_DATA,
>DENALI_PHY_1082_DATA,
>> + DENALI_PHY_1083_DATA, DENALI_PHY_1084_DATA,
>DENALI_PHY_1085_DATA,
>> + DENALI_PHY_1086_DATA, DENALI_PHY_1087_DATA,
>DENALI_PHY_1088_DATA,
>> + DENALI_PHY_1089_DATA,
>> + DENALI_PHY_1090_DATA, DENALI_PHY_1091_DATA,
>DENALI_PHY_1092_DATA,
>> + DENALI_PHY_1093_DATA, DENALI_PHY_1094_DATA,
>DENALI_PHY_1095_DATA,
>> + DENALI_PHY_1096_DATA, DENALI_PHY_1097_DATA,
>DENALI_PHY_1098_DATA,
>> + DENALI_PHY_1099_DATA,
>> +
>> + DENALI_PHY_1100_DATA, DENALI_PHY_1101_DATA,
>DENALI_PHY_1102_DATA,
>> + DENALI_PHY_1103_DATA, DENALI_PHY_1104_DATA,
>DENALI_PHY_1105_DATA,
>> + DENALI_PHY_1106_DATA, DENALI_PHY_1107_DATA,
>DENALI_PHY_1108_DATA,
>> + DENALI_PHY_1109_DATA,
>> + DENALI_PHY_1110_DATA, DENALI_PHY_1111_DATA,
>DENALI_PHY_1112_DATA,
>> + DENALI_PHY_1113_DATA, DENALI_PHY_1114_DATA,
>DENALI_PHY_1115_DATA,
>> + DENALI_PHY_1116_DATA, DENALI_PHY_1117_DATA,
>DENALI_PHY_1118_DATA,
>> + DENALI_PHY_1119_DATA,
>> + DENALI_PHY_1120_DATA, DENALI_PHY_1121_DATA,
>DENALI_PHY_1122_DATA,
>> + DENALI_PHY_1123_DATA, DENALI_PHY_1124_DATA,
>DENALI_PHY_1125_DATA,
>> + DENALI_PHY_1126_DATA, DENALI_PHY_1127_DATA,
>DENALI_PHY_1128_DATA,
>> + DENALI_PHY_1129_DATA,
>> + DENALI_PHY_1130_DATA, DENALI_PHY_1131_DATA,
>DENALI_PHY_1132_DATA,
>> + DENALI_PHY_1133_DATA, DENALI_PHY_1134_DATA,
>DENALI_PHY_1135_DATA,
>> + DENALI_PHY_1136_DATA, DENALI_PHY_1137_DATA,
>DENALI_PHY_1138_DATA,
>> + DENALI_PHY_1139_DATA,
>> + DENALI_PHY_1140_DATA, DENALI_PHY_1141_DATA,
>DENALI_PHY_1142_DATA,
>> + DENALI_PHY_1143_DATA, DENALI_PHY_1144_DATA,
>DENALI_PHY_1145_DATA,
>> + DENALI_PHY_1146_DATA, DENALI_PHY_1147_DATA,
>DENALI_PHY_1148_DATA,
>> + DENALI_PHY_1149_DATA,
>> + DENALI_PHY_1150_DATA, DENALI_PHY_1151_DATA,
>DENALI_PHY_1152_DATA,
>> + DENALI_PHY_1153_DATA, DENALI_PHY_1154_DATA,
>DENALI_PHY_1155_DATA,
>> + DENALI_PHY_1156_DATA, DENALI_PHY_1157_DATA,
>DENALI_PHY_1158_DATA,
>> + DENALI_PHY_1159_DATA,
>> + DENALI_PHY_1160_DATA, DENALI_PHY_1161_DATA,
>DENALI_PHY_1162_DATA,
>> + DENALI_PHY_1163_DATA, DENALI_PHY_1164_DATA,
>DENALI_PHY_1165_DATA,
>> + DENALI_PHY_1166_DATA, DENALI_PHY_1167_DATA,
>DENALI_PHY_1168_DATA,
>> + DENALI_PHY_1169_DATA,
>> + DENALI_PHY_1170_DATA, DENALI_PHY_1171_DATA,
>DENALI_PHY_1172_DATA,
>> + DENALI_PHY_1173_DATA, DENALI_PHY_1174_DATA,
>DENALI_PHY_1175_DATA,
>> + DENALI_PHY_1176_DATA, DENALI_PHY_1177_DATA,
>DENALI_PHY_1178_DATA,
>> + DENALI_PHY_1179_DATA,
>> + DENALI_PHY_1180_DATA, DENALI_PHY_1181_DATA,
>DENALI_PHY_1182_DATA,
>> + DENALI_PHY_1183_DATA, DENALI_PHY_1184_DATA,
>DENALI_PHY_1185_DATA,
>> + DENALI_PHY_1186_DATA, DENALI_PHY_1187_DATA,
>DENALI_PHY_1188_DATA,
>> + DENALI_PHY_1189_DATA,
>> + DENALI_PHY_1190_DATA, DENALI_PHY_1191_DATA,
>DENALI_PHY_1192_DATA,
>> + DENALI_PHY_1193_DATA, DENALI_PHY_1194_DATA,
>DENALI_PHY_1195_DATA,
>> + DENALI_PHY_1196_DATA, DENALI_PHY_1197_DATA,
>DENALI_PHY_1198_DATA,
>> + DENALI_PHY_1199_DATA,
>> +
>> + DENALI_PHY_1200_DATA, DENALI_PHY_1201_DATA,
>DENALI_PHY_1202_DATA,
>> + DENALI_PHY_1203_DATA, DENALI_PHY_1204_DATA,
>DENALI_PHY_1205_DATA,
>> + DENALI_PHY_1206_DATA, DENALI_PHY_1207_DATA,
>DENALI_PHY_1208_DATA,
>> + DENALI_PHY_1209_DATA,
>> + DENALI_PHY_1210_DATA, DENALI_PHY_1211_DATA,
>DENALI_PHY_1212_DATA,
>> + DENALI_PHY_1213_DATA, DENALI_PHY_1214_DATA
>> +};
>> +
>> +u32 DENALI_CTL_DATA[265] = {
>> + DENALI_CTL_00_DATA, DENALI_CTL_01_DATA, DENALI_CTL_02_DATA,
>> + DENALI_CTL_03_DATA, DENALI_CTL_04_DATA, DENALI_CTL_05_DATA,
>> + DENALI_CTL_06_DATA, DENALI_CTL_07_DATA, DENALI_CTL_08_DATA,
>> + DENALI_CTL_09_DATA,
>> + DENALI_CTL_10_DATA, DENALI_CTL_11_DATA, DENALI_CTL_12_DATA,
>> + DENALI_CTL_13_DATA, DENALI_CTL_14_DATA, DENALI_CTL_15_DATA,
>> + DENALI_CTL_16_DATA, DENALI_CTL_17_DATA, DENALI_CTL_18_DATA,
>> + DENALI_CTL_19_DATA,
>> + DENALI_CTL_20_DATA, DENALI_CTL_21_DATA, DENALI_CTL_22_DATA,
>> + DENALI_CTL_23_DATA, DENALI_CTL_24_DATA, DENALI_CTL_25_DATA,
>> + DENALI_CTL_26_DATA, DENALI_CTL_27_DATA, DENALI_CTL_28_DATA,
>> + DENALI_CTL_29_DATA,
>> + DENALI_CTL_30_DATA, DENALI_CTL_31_DATA, DENALI_CTL_32_DATA,
>> + DENALI_CTL_33_DATA, DENALI_CTL_34_DATA, DENALI_CTL_35_DATA,
>> + DENALI_CTL_36_DATA, DENALI_CTL_37_DATA, DENALI_CTL_38_DATA,
>> + DENALI_CTL_39_DATA,
>> + DENALI_CTL_40_DATA, DENALI_CTL_41_DATA, DENALI_CTL_42_DATA,
>> + DENALI_CTL_43_DATA, DENALI_CTL_44_DATA, DENALI_CTL_45_DATA,
>> + DENALI_CTL_46_DATA, DENALI_CTL_47_DATA, DENALI_CTL_48_DATA,
>> + DENALI_CTL_49_DATA,
>> + DENALI_CTL_50_DATA, DENALI_CTL_51_DATA, DENALI_CTL_52_DATA,
>> + DENALI_CTL_53_DATA, DENALI_CTL_54_DATA, DENALI_CTL_55_DATA,
>> + DENALI_CTL_56_DATA, DENALI_CTL_57_DATA, DENALI_CTL_58_DATA,
>> + DENALI_CTL_59_DATA,
>> + DENALI_CTL_60_DATA, DENALI_CTL_61_DATA, DENALI_CTL_62_DATA,
>> + DENALI_CTL_63_DATA, DENALI_CTL_64_DATA, DENALI_CTL_65_DATA,
>> + DENALI_CTL_66_DATA, DENALI_CTL_67_DATA, DENALI_CTL_68_DATA,
>> + DENALI_CTL_69_DATA,
>> + DENALI_CTL_70_DATA, DENALI_CTL_71_DATA, DENALI_CTL_72_DATA,
>> + DENALI_CTL_73_DATA, DENALI_CTL_74_DATA, DENALI_CTL_75_DATA,
>> + DENALI_CTL_76_DATA, DENALI_CTL_77_DATA, DENALI_CTL_78_DATA,
>> + DENALI_CTL_79_DATA,
>> + DENALI_CTL_80_DATA, DENALI_CTL_81_DATA, DENALI_CTL_82_DATA,
>> + DENALI_CTL_83_DATA, DENALI_CTL_84_DATA, DENALI_CTL_85_DATA,
>> + DENALI_CTL_86_DATA, DENALI_CTL_87_DATA, DENALI_CTL_88_DATA,
>> + DENALI_CTL_89_DATA,
>> + DENALI_CTL_90_DATA, DENALI_CTL_91_DATA, DENALI_CTL_92_DATA,
>> + DENALI_CTL_93_DATA, DENALI_CTL_94_DATA, DENALI_CTL_95_DATA,
>> + DENALI_CTL_96_DATA, DENALI_CTL_97_DATA, DENALI_CTL_98_DATA,
>> + DENALI_CTL_99_DATA,
>> +
>> + DENALI_CTL_100_DATA, DENALI_CTL_101_DATA,
>DENALI_CTL_102_DATA,
>> + DENALI_CTL_103_DATA, DENALI_CTL_104_DATA,
>DENALI_CTL_105_DATA,
>> + DENALI_CTL_106_DATA, DENALI_CTL_107_DATA,
>DENALI_CTL_108_DATA,
>> + DENALI_CTL_109_DATA,
>> + DENALI_CTL_110_DATA, DENALI_CTL_111_DATA,
>DENALI_CTL_112_DATA,
>> + DENALI_CTL_113_DATA, DENALI_CTL_114_DATA,
>DENALI_CTL_115_DATA,
>> + DENALI_CTL_116_DATA, DENALI_CTL_117_DATA,
>DENALI_CTL_118_DATA,
>> + DENALI_CTL_119_DATA,
>> + DENALI_CTL_120_DATA, DENALI_CTL_121_DATA,
>DENALI_CTL_122_DATA,
>> + DENALI_CTL_123_DATA, DENALI_CTL_124_DATA,
>DENALI_CTL_125_DATA,
>> + DENALI_CTL_126_DATA, DENALI_CTL_127_DATA,
>DENALI_CTL_128_DATA,
>> + DENALI_CTL_129_DATA,
>> + DENALI_CTL_130_DATA, DENALI_CTL_131_DATA,
>DENALI_CTL_132_DATA,
>> + DENALI_CTL_133_DATA, DENALI_CTL_134_DATA,
>DENALI_CTL_135_DATA,
>> + DENALI_CTL_136_DATA, DENALI_CTL_137_DATA,
>DENALI_CTL_138_DATA,
>> + DENALI_CTL_139_DATA,
>> + DENALI_CTL_140_DATA, DENALI_CTL_141_DATA,
>DENALI_CTL_142_DATA,
>> + DENALI_CTL_143_DATA, DENALI_CTL_144_DATA,
>DENALI_CTL_145_DATA,
>> + DENALI_CTL_146_DATA, DENALI_CTL_147_DATA,
>DENALI_CTL_148_DATA,
>> + DENALI_CTL_149_DATA,
>> + DENALI_CTL_150_DATA, DENALI_CTL_151_DATA,
>DENALI_CTL_152_DATA,
>> + DENALI_CTL_153_DATA, DENALI_CTL_154_DATA,
>DENALI_CTL_155_DATA,
>> + DENALI_CTL_156_DATA, DENALI_CTL_157_DATA,
>DENALI_CTL_158_DATA,
>> + DENALI_CTL_159_DATA,
>> + DENALI_CTL_160_DATA, DENALI_CTL_161_DATA,
>DENALI_CTL_162_DATA,
>> + DENALI_CTL_163_DATA, DENALI_CTL_164_DATA,
>DENALI_CTL_165_DATA,
>> + DENALI_CTL_166_DATA, DENALI_CTL_167_DATA,
>DENALI_CTL_168_DATA,
>> + DENALI_CTL_169_DATA,
>> + DENALI_CTL_170_DATA, DENALI_CTL_171_DATA,
>DENALI_CTL_172_DATA,
>> + DENALI_CTL_173_DATA, DENALI_CTL_174_DATA,
>DENALI_CTL_175_DATA,
>> + DENALI_CTL_176_DATA, DENALI_CTL_177_DATA,
>DENALI_CTL_178_DATA,
>> + DENALI_CTL_179_DATA,
>> + DENALI_CTL_180_DATA, DENALI_CTL_181_DATA,
>DENALI_CTL_182_DATA,
>> + DENALI_CTL_183_DATA, DENALI_CTL_184_DATA,
>DENALI_CTL_185_DATA,
>> + DENALI_CTL_186_DATA, DENALI_CTL_187_DATA,
>DENALI_CTL_188_DATA,
>> + DENALI_CTL_189_DATA,
>> + DENALI_CTL_190_DATA, DENALI_CTL_191_DATA,
>DENALI_CTL_192_DATA,
>> + DENALI_CTL_193_DATA, DENALI_CTL_194_DATA,
>DENALI_CTL_195_DATA,
>> + DENALI_CTL_196_DATA, DENALI_CTL_197_DATA,
>DENALI_CTL_198_DATA,
>> + DENALI_CTL_199_DATA,
>> +
>> + DENALI_CTL_200_DATA, DENALI_CTL_201_DATA,
>DENALI_CTL_202_DATA,
>> + DENALI_CTL_203_DATA, DENALI_CTL_204_DATA,
>DENALI_CTL_205_DATA,
>> + DENALI_CTL_206_DATA, DENALI_CTL_207_DATA,
>DENALI_CTL_208_DATA,
>> + DENALI_CTL_209_DATA,
>> + DENALI_CTL_210_DATA, DENALI_CTL_211_DATA,
>DENALI_CTL_212_DATA,
>> + DENALI_CTL_213_DATA, DENALI_CTL_214_DATA,
>DENALI_CTL_215_DATA,
>> + DENALI_CTL_216_DATA, DENALI_CTL_217_DATA,
>DENALI_CTL_218_DATA,
>> + DENALI_CTL_219_DATA,
>> + DENALI_CTL_220_DATA, DENALI_CTL_221_DATA,
>DENALI_CTL_222_DATA,
>> + DENALI_CTL_223_DATA, DENALI_CTL_224_DATA,
>DENALI_CTL_225_DATA,
>> + DENALI_CTL_226_DATA, DENALI_CTL_227_DATA,
>DENALI_CTL_228_DATA,
>> + DENALI_CTL_229_DATA,
>> + DENALI_CTL_230_DATA, DENALI_CTL_231_DATA,
>DENALI_CTL_232_DATA,
>> + DENALI_CTL_233_DATA, DENALI_CTL_234_DATA,
>DENALI_CTL_235_DATA,
>> + DENALI_CTL_236_DATA, DENALI_CTL_237_DATA,
>DENALI_CTL_238_DATA,
>> + DENALI_CTL_239_DATA,
>> + DENALI_CTL_240_DATA, DENALI_CTL_241_DATA,
>DENALI_CTL_242_DATA,
>> + DENALI_CTL_243_DATA, DENALI_CTL_244_DATA,
>DENALI_CTL_245_DATA,
>> + DENALI_CTL_246_DATA, DENALI_CTL_247_DATA,
>DENALI_CTL_248_DATA,
>> + DENALI_CTL_249_DATA,
>> + DENALI_CTL_250_DATA, DENALI_CTL_251_DATA,
>DENALI_CTL_252_DATA,
>> + DENALI_CTL_253_DATA, DENALI_CTL_254_DATA,
>DENALI_CTL_255_DATA,
>> + DENALI_CTL_256_DATA, DENALI_CTL_257_DATA,
>DENALI_CTL_258_DATA,
>> + DENALI_CTL_259_DATA,
>> + DENALI_CTL_260_DATA, DENALI_CTL_261_DATA,
>DENALI_CTL_262_DATA,
>> + DENALI_CTL_263_DATA, DENALI_CTL_264_DATA
>> +};
>
>Can this handle to write separate driver for ram like drivers/ram ?
I didn't get you.
>> diff --git a/board/sifive/fu540/include/ememoryotp.h
>b/board/sifive/fu540/include/ememoryotp.h
>> new file mode 100644
>> index 0000000000..274283c4db
>> --- /dev/null
>> +++ b/board/sifive/fu540/include/ememoryotp.h
>> @@ -0,0 +1,24 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (c) 2019 SiFive, Inc
>> + *
>> + * Authors:
>> + * Pragnesh Patel <pragnesh.patel at sifive.com>
>> + * Troy Benjegerdes <troy.benjegerdes at sifive.com>
>> + */
>> +
[...]
>> +
>> +#ifndef __ASSEMBLER__
>> +
>> +#include <stdint.h>
>> +#include <stddef.h>
>> +#include <stdbool.h>
>> +#include "uart.h"
>> +#include "fu540-memory-map.h"
>> +
>> +#define DRAM_CLASS_OFFSET 8
>> +#define DRAM_CLASS_DDR4 0xA
>> +#define OPTIMAL_RMODW_EN_OFFSET 0
>> +#define DISABLE_RD_INTERLEAVE_OFFSET 16
>> +#define OUT_OF_RANGE_OFFSET 1
>> +#define MULTIPLE_OUT_OF_RANGE_OFFSET 2
>> +#
>
>Sorry, too much stuff in single patch. it is worth require multiple patches.
Sure, will split this into multiple patches.
>
>Jagan.
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