[PATCH v2 01/19] i2c: designware_i2c: Add more registers
pt
ptchentw at gmail.com
Wed Jan 8 03:27:14 CET 2020
Hi,
There is a gap from "clr_restart_det" 0xa8 to "comp_param1" 0xf4,
you should reserve a space for them.
Best regards,
Jun Chen
Simon Glass <sjg at chromium.org> 於 2020年1月4日 週六 上午6:27寫道:
> Some versions of this peripherals provide more control of the bus
> behaviour. Add definitions for these registers.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> Reviewed-by: Ley Foon Tan <ley.foon.tan at intel.com>
> Reviewed-by: Jun Chen <ptchentw at gmail.com>
> ---
>
> Changes in v2:
> - Fix 'previde' typo
>
> drivers/i2c/designware_i2c.h | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h
> index 48766d0806..d359c8c3f8 100644
> --- a/drivers/i2c/designware_i2c.h
> +++ b/drivers/i2c/designware_i2c.h
> @@ -43,8 +43,19 @@ struct i2c_regs {
> u32 ic_rxflr; /* 0x78 */
> u32 ic_sda_hold; /* 0x7c */
> u32 ic_tx_abrt_source; /* 0x80 */
> - u8 res1[0x18]; /* 0x84 */
> + u32 slv_data_nak_only;
> + u32 dma_cr;
> + u32 dma_tdlr;
> + u32 dma_rdlr;
> + u32 sda_setup;
> + u32 ack_general_call;
> u32 ic_enable_status; /* 0x9c */
> + u32 fs_spklen;
> + u32 hs_spklen;
> + u32 clr_restart_det;
>
There is a gap here.
> + u32 comp_param1;
> + u32 comp_version;
> + u32 comp_type;
> };
>
> #if !defined(IC_CLK)
> --
> 2.24.1.735.g03f4e72817-goog
>
>
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