[PATCH v5] reset: socfpga: Poll for reset status after deassert reset

[Ley Foon Tan]

In Cyclone 5 SoC platform, the first USB probing is failed but second
probing is success. DWC2 USB driver read gsnpsid register right after
de-assert reset, but controller is not ready yet and it returns gsnpsid 0.
Polling reset status after de-assert reset to solve the issue.

Retry with this fix more than 10 times without issue.

Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>

---
v5:
- Change to use wait_for_bit_le32().

v4:
- Change to use get_timer() for timeout.
- https://patchwork.ozlabs.org/patch/1219487/

v3:
- Remove _status callback and poll reset status after deassert reset
- https://patchwork.ozlabs.org/patch/1218026/

v2:
- https://patchwork.ozlabs.org/cover/1215174/

v1:
- https://patchwork.ozlabs.org/patch/1214841/
---
 drivers/reset/reset-socfpga.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index 93ec9cfdb6..105ce94c71 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -18,6 +18,7 @@
 #include <dm/of_access.h>
 #include <env.h>
 #include <reset-uclass.h>
+#include <wait_bit.h>
 #include <linux/bitops.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
@@ -80,7 +81,10 @@ static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
 	int offset = id % (reg_width * BITS_PER_BYTE);
 
 	clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
-	return 0;
+
+	return wait_for_bit_le32(data->modrst_base + (bank * BANK_INCREMENT),
+				 BIT(offset),
+				 false, 500, false);
 }
 
 static int socfpga_reset_request(struct reset_ctl *reset_ctl)
-- 
2.19.0