[PATCH v2 8/9] riscv: sifive: fu540: add SPL configuration
Pragnesh Patel
pragnesh.patel at sifive.com
Mon Jan 20 12:16:04 CET 2020
Hi Anup,
>-----Original Message-----
>From: Anup Patel <anup at brainfault.org>
>Sent: 20 January 2020 11:35
>To: Pragnesh Patel <pragnesh.patel at sifive.com>
>Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Palmer Dabbelt
><palmerdabbelt at google.com>; Atish Patra <atish.patra at wdc.com>; Palmer
>Dabbelt ( Sifive) <palmer at sifive.com>
>Subject: Re: [PATCH v2 8/9] riscv: sifive: fu540: add SPL configuration
>
>On Fri, Jan 17, 2020 at 6:18 PM Pragnesh Patel
><pragnesh.patel at sifive.com> wrote:
>>
>> This patch provides sifive_fu540_spl_defconfig which can support
>> U-boot SPL to boot from L2 LIM (0x0800_0000) and then boot U-boot
>> FIT image including OpenSBI FW_DYNAMIC firmware and U-Boot proper
>> images from MMC boot devices.
>>
>> With sifive_fu540_spl_defconfig:
>>
>> U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
>> u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
>> image u-boot.itb from SD card (replace fw_payload.bin with u-boot.itb)
>> into RAM.
>>
>> SPL related code is leverage from FSBL
>> (https://github.com/sifive/freedom-u540-c000-bootloader.git)
>
>Please look at my comments in PATCH7 regarding patch break-up.
>
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
>> ---
>> arch/riscv/include/asm/csr.h | 2 +
>> board/sifive/fu540/Kconfig | 8 +
>> board/sifive/fu540/MAINTAINERS | 1 +
>> board/sifive/fu540/Makefile | 5 +
>> board/sifive/fu540/ddrregs.c | 625 +++++++++++++++++++++++++++++
>> board/sifive/fu540/fu540.c | 27 +-
>> board/sifive/fu540/spl.c | 307 ++++++++++++++
>> configs/sifive_fu540_spl_defconfig | 26 ++
>> include/configs/sifive-fu540.h | 18 +
>> 9 files changed, 1018 insertions(+), 1 deletion(-)
>> create mode 100644 board/sifive/fu540/ddrregs.c
>> create mode 100644 board/sifive/fu540/spl.c
>> create mode 100644 configs/sifive_fu540_spl_defconfig
>>
>> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
>> index d1520743a2..125c05dd8a 100644
>> --- a/arch/riscv/include/asm/csr.h
>> +++ b/arch/riscv/include/asm/csr.h
>> @@ -103,6 +103,8 @@
>> #define CSR_TIMEH 0xc81
>> #define CSR_INSTRETH 0xc82
>> #define CSR_MHARTID 0xf14
>> +#define CSR_MCYCLE 0xb00
>> +#define CSR_MCYCLEH 0xb80
>
>This is a totally unrelated change. Please remove this change OR
>send it as separate patch.
I will remove this in v3, thanks.
>
>>
>> #ifndef __ASSEMBLY__
>>
>> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
>> index 816a135b21..ac7c6bff37 100644
>> --- a/board/sifive/fu540/Kconfig
>> +++ b/board/sifive/fu540/Kconfig
>> @@ -16,12 +16,20 @@ config SYS_SOC
>> default "fu540"
>>
>> config SYS_TEXT_BASE
>> + default 0x80200000 if SPL
>> default 0x80000000 if !RISCV_SMODE
>> default 0x80200000 if RISCV_SMODE
>>
>> +config SPL_TEXT_BASE
>> + default 0x08000000
>> +
>> +config SPL_OPENSBI_LOAD_ADDR
>> + default 0x80000000
>> +
>> config BOARD_SPECIFIC_OPTIONS # dummy
>> def_bool y
>> select GENERIC_RISCV
>> + select SUPPORT_SPL
>> imply CMD_DHCP
>> imply CMD_EXT2
>> imply CMD_EXT4
>> diff --git a/board/sifive/fu540/MAINTAINERS
>b/board/sifive/fu540/MAINTAINERS
>> index 702d803ad8..42c3f3deb0 100644
>> --- a/board/sifive/fu540/MAINTAINERS
>> +++ b/board/sifive/fu540/MAINTAINERS
>> @@ -7,3 +7,4 @@ S: Maintained
>> F: board/sifive/fu540/
>> F: include/configs/sifive-fu540.h
>> F: configs/sifive_fu540_defconfig
>> +F: configs/sifive_fu540_spl_defconfig
>
>Palmer's email address is incorrect in this file.
>
>I suggest to have separate patch for updating fu540/MAINTAINERS
>file and not change fu540/MAINTAINERS here:
>1. Add configs/sifive_fu540_spl_defconfig
>2. Update Palmer's email address
>3. Add yourself as first/primary maintainer for sifive/fu540 board support.
>Other folks (including Me and Atish) are busy with other things so they
>we are slow on U-Boot patch reviewes.
Will update fu540/MAINTAINERS and add a separate patch in v3.
>
>> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
>> index 6e1862c475..f01e731913 100644
>> --- a/board/sifive/fu540/Makefile
>> +++ b/board/sifive/fu540/Makefile
>> @@ -3,3 +3,8 @@
>> # Copyright (c) 2019 Western Digital Corporation or its affiliates.
>>
>> obj-y += fu540.o
>> +
>> +ifdef CONFIG_SPL_BUILD
>> +obj-y += spl.o
>> +obj-y += ddrregs.o
>> +endif
>> diff --git a/board/sifive/fu540/ddrregs.c b/board/sifive/fu540/ddrregs.c
>> new file mode 100644
>> index 0000000000..5c9c238aa1
>> --- /dev/null
>> +++ b/board/sifive/fu540/ddrregs.c
>> @@ -0,0 +1,625 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (c) 2019 SiFive, Inc
>> + *
>> + * Authors:
>> + * Pragnesh Patel <pragnesh.patel at sifive.com>
>> + * Troy Benjegerdes <troy.benjegerdes at sifive.com>
>> + */
>> +
>> +#include <common.h>
>> +
>> +#include "regconfig-ctl.h"
>> +#include "regconfig-phy.h"
>> +
>> +u32 ddr_phy_settings[1215] = {
>> + DENALI_PHY_00_DATA, DENALI_PHY_01_DATA,
>DENALI_PHY_02_DATA,
>> + DENALI_PHY_03_DATA, DENALI_PHY_04_DATA,
>DENALI_PHY_05_DATA,
>> + DENALI_PHY_06_DATA, DENALI_PHY_07_DATA,
>DENALI_PHY_08_DATA,
>> + DENALI_PHY_09_DATA,
>> + DENALI_PHY_10_DATA, DENALI_PHY_11_DATA,
>DENALI_PHY_12_DATA,
>> + DENALI_PHY_13_DATA, DENALI_PHY_14_DATA,
>DENALI_PHY_15_DATA,
>> + DENALI_PHY_16_DATA, DENALI_PHY_17_DATA,
>DENALI_PHY_18_DATA,
>> + DENALI_PHY_19_DATA,
>> + DENALI_PHY_20_DATA, DENALI_PHY_21_DATA,
>> [....]
>> 2.17.1
>>
>
>Regards,
>Anup
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