[PATCH v3 08/10] riscv: sifive: fu540: enable all cache ways from u-boot proper
Anup Patel
anup at brainfault.org
Sat Jan 25 09:36:56 CET 2020
On Fri, Jan 24, 2020 at 11:22 AM Pragnesh Patel
<pragnesh.patel at sifive.com> wrote:
>
> This patch enables all cache ways from u-boot proper.
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
> ---
> board/sifive/fu540/Makefile | 1 +
> board/sifive/fu540/cache.c | 30 ++++++++++++++++++++++++++++++
> board/sifive/fu540/cache.h | 13 +++++++++++++
> board/sifive/fu540/fu540.c | 6 ++++--
> 4 files changed, 48 insertions(+), 2 deletions(-)
> create mode 100644 board/sifive/fu540/cache.c
> create mode 100644 board/sifive/fu540/cache.h
>
> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
> index cdcf894ade..a79928a0bf 100644
> --- a/board/sifive/fu540/Makefile
> +++ b/board/sifive/fu540/Makefile
> @@ -3,6 +3,7 @@
> # Copyright (c) 2019 Western Digital Corporation or its affiliates.
>
> obj-y += fu540.o
> +obj-y += cache.o
>
> ifdef CONFIG_SPL_BUILD
> obj-y += spl.o
> diff --git a/board/sifive/fu540/cache.c b/board/sifive/fu540/cache.c
> new file mode 100644
> index 0000000000..c91728a678
> --- /dev/null
> +++ b/board/sifive/fu540/cache.c
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +#include <stdint.h>
> +#include <linux/types.h>
> +
> +/* Register offsets */
> +#define CACHE_ENABLE 0x008
> +
> +/* Block memory access until operation completed */
> +static void cache_barrier_0(void)
> +{
> + asm volatile("fence rw, io" : : : "memory");
> +}
> +
> +static void cache_barrier_1(void)
> +{
> + asm volatile("fence io, rw" : : : "memory");
> +}
> +
> +/* Enable ways; allow cache to use these ways */
> +void cache_enable_ways(u64 base_addr, u8 value)
> +{
> + volatile u32 *enable = (volatile u32 *)(base_addr +
> + CACHE_ENABLE);
> + cache_barrier_0();
> + (*enable) = value;
> + cache_barrier_1();
> +}
> diff --git a/board/sifive/fu540/cache.h b/board/sifive/fu540/cache.h
> new file mode 100644
> index 0000000000..425124a23b
> --- /dev/null
> +++ b/board/sifive/fu540/cache.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +
> +#ifndef FU540_CACHE_H
> +#define FU540_CACHE_H
> +
> +#define CACHE_CTRL_ADDR _AC(0x2010000, UL)
> +
> +void cache_enable_ways(u64 base_addr, u8 value);
> +
> +#endif /* FU540_CACHE_H */
> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
> index b81003aa6f..7fde881e72 100644
> --- a/board/sifive/fu540/fu540.c
> +++ b/board/sifive/fu540/fu540.c
> @@ -13,6 +13,8 @@
> #include <misc.h>
> #include <spl.h>
>
> +#include "cache.h"
> +
> /*
> * This define is a value used for error/unknown serial.
> * If we really care about distinguishing errors and 0 is
> @@ -111,8 +113,8 @@ int misc_init_r(void)
>
> int board_init(void)
> {
> - /* For now nothing to do here. */
> -
> + /* enable all cache ways */
> + cache_enable_ways(CACHE_CTRL_ADDR, 15);
> return 0;
> }
>
> --
> 2.17.1
>
LGTM.
Reviewed-by: Anup Patel <anup.patel at wdc.com>
Regards,
Anup
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