[PATCH v1 3/5] board: toradex: add Verdin iMX8MM 2GB WB IT v1.0a
Marcel Ziswiler
marcel.ziswiler at toradex.com
Sun Jan 26 02:01:06 CET 2020
Hi Igor
On Thu, 2020-01-23 at 13:31 +0200, Igor Opaniuk wrote:
> From: Igor Opaniuk <igor.opaniuk at toradex.com>
>
> This introduces initial support for the Toradex Verdin iMX8MM 2GB WB
> IT
> V1.0A module. They are now strapped to boot from eFuses which are
> factory fused to properly boot from their on-module eMMC. U-Boot
> supports booting from the on-module eMMC only, SDP support is
> disabled
> for now.
>
> Functionality wise the following is known to be working:
> - eMMC, 8-bit and 4-bit MMC/SD card slots
> - Ethernet
> - GPIOs
> - I2C
>
> Boot sequence is:
> SPL ---> ATF (TF-A) ---> U-boot proper
>
> ATF, U-boot proper and u-boot.dtb images are packed into FIT image,
> loaded by SPL.
>
> U-Boot SPL 2020.01-01840-gd92bdc79cf-dirty (Jan 22 2020 - 18:50:57
> +0200)
> Normal Boot
> Trying to boot from MMC1
>
> U-Boot 2020.01-01840-gd92bdc79cf-dirty (Jan 22 2020 - 18:50:57 +0200)
>
> CPU: Freescale i.MX8MMQ rev1.0 at 0 MHz
> Reset cause: POR
> DRAM: 2 GiB
> MMC: FSL_SDHC: 0, FSL_SDHC: 1
> Loading Environment from MMC... OK
> In: serial
> Out: serial
> Err: serial
> Model: Toradex Verdin iMX8M Mini 2GB Wi-Fi / BT IT V1.0A, Serial#
> 06535148
> Net: Could not get PHY for FEC0: addr 7
> eth0: ethernet at 30be0000
> Hit any key to stop autoboot: 0
>
> Signed-off-by: Igor Opaniuk <igor.opaniuk at toradex.com>
> Signed-off-by: Max Krummenacher <max.krummenacher at toradex.com>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler at toradex.com>
> ---
>
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/imx8mm-verdin-u-boot.dtsi | 103 ++
> arch/arm/dts/imx8mm-verdin.dts | 854 +++++++++
> arch/arm/mach-imx/imx8m/Kconfig | 7 +
> board/toradex/verdin-imx8mm/Kconfig | 30 +
> board/toradex/verdin-imx8mm/Makefile | 12 +
> board/toradex/verdin-imx8mm/imximage.cfg | 16 +
> board/toradex/verdin-imx8mm/lpddr4_timing.c | 1851
> +++++++++++++++++++
> board/toradex/verdin-imx8mm/spl.c | 183 ++
> board/toradex/verdin-imx8mm/verdin-imx8mm.c | 74 +
> configs/verdin-imx8mm_defconfig | 88 +
> include/configs/verdin-imx8mm.h | 121 ++
> 12 files changed, 3341 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/imx8mm-verdin-u-boot.dtsi
> create mode 100644 arch/arm/dts/imx8mm-verdin.dts
> create mode 100644 board/toradex/verdin-imx8mm/Kconfig
> create mode 100644 board/toradex/verdin-imx8mm/Makefile
> create mode 100644 board/toradex/verdin-imx8mm/imximage.cfg
> create mode 100644 board/toradex/verdin-imx8mm/lpddr4_timing.c
> create mode 100644 board/toradex/verdin-imx8mm/spl.c
> create mode 100644 board/toradex/verdin-imx8mm/verdin-imx8mm.c
> create mode 100644 configs/verdin-imx8mm_defconfig
> create mode 100644 include/configs/verdin-imx8mm.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 44f742017e..4c5ae923e4 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -711,7 +711,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
> imx8mm-evk.dtb \
> imx8mn-ddr4-evk.dtb \
> imx8mq-evk.dtb \
> - imx8mp-evk.dtb
> + imx8mp-evk.dtb \
> + imx8mm-verdin.dtb
We should preserve the alphabetical order.
> dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb
>
> diff --git a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
> b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
> new file mode 100644
> index 0000000000..628d9af151
> --- /dev/null
> +++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
> @@ -0,0 +1,103 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
I don't think any parentheses are needed.
> +/*
> + * Copyright 2019 Toradex AG
It's already 2020 now (;-p).
> + */
> +
> +&{/soc at 0} {
> + u-boot,dm-pre-reloc;
> + u-boot,dm-spl;
> +};
> +
> +&clk {
> + u-boot,dm-spl;
> + u-boot,dm-pre-reloc;
> + /delete-property/ assigned-clocks;
> + /delete-property/ assigned-clock-parents;
> + /delete-property/ assigned-clock-rates;
> +};
> +
> +&osc_24m {
> + u-boot,dm-spl;
> + u-boot,dm-pre-reloc;
> +};
> +
> +&aips1 {
> + u-boot,dm-spl;
> + u-boot,dm-pre-reloc;
> +};
> +
> +&aips2 {
> + u-boot,dm-spl;
> +};
> +
> +&aips3 {
> + u-boot,dm-spl;
> +};
> +
> +&iomuxc {
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl_uart1 {
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl_usdhc2 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio1 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio2 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio3 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio4 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio5 {
> + u-boot,dm-spl;
> +};
> +
> +&uart1 {
> + u-boot,dm-spl;
> +};
> +
> +&usdhc1 {
> + u-boot,dm-spl;
> +};
> +
> +&usdhc2 {
> + u-boot,dm-spl;
> +};
> +
> +&usdhc3 {
> + u-boot,dm-spl;
> +};
> +
> +&i2c1 {
> + u-boot,dm-spl;
> +};
> +
> +&{/soc at 0/bus at 30800000/i2c at 30a20000/pmic at 4b} {
> + u-boot,dm-spl;
> +};
> +
> +&{/soc at 0/bus at 30800000/i2c at 30a20000/pmic at 4b/regulators} {
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl_i2c1 {
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl_pmic {
> + u-boot,dm-spl;
> +};
I guess also the U-Boot specific device tree should adhere to
alphabetical node ordering.
> diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-
> verdin.dts
> new file mode 100644
> index 0000000000..b450057d3a
> --- /dev/null
> +++ b/arch/arm/dts/imx8mm-verdin.dts
> @@ -0,0 +1,854 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2019 Toradex AG
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/usb/pd.h>
> +#include "imx8mm.dtsi"
> +
> +/ {
> + model = "Toradex Verdin iMX8MM";
> + compatible = "toradex,verdin-imx8mm", "fsl,imx8mm";
> +
> + chosen {
> + stdout-path = &uart1;
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
This simple-bus stuff is ancient and has no space in mainline any
longer.
> + reg_ethphy: regulator-ethphy {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_eth>;
> + regulator-name = "V3.3_ETH";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_usdhc2_vmmc: regulator-usdhc2 {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
> + regulator-name = "V3.3_SD";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
> + startup-delay-us = <2000>;
> + enable-active-high;
> + };
> +
> + reg_usb_otg1_vbus: regulator-usb-otg1 {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_usb1_en>;
> + regulator-name = "usb_otg1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + /* Verdin USB1_EN */
> + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
> + };
> +
> + reg_usb_otg2_vbus: regulator-usb-otg2 {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_usb2_en>;
> + regulator-name = "usb_otg2_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + /* Verdin USB2_EN */
> + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +};
> +
> +&A53_0 {
> + cpu-supply = <&buck2_reg>;
> +};
> +
> +&clk {
> + assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, <&clk
> IMX8MM_AUDIO_PLL2>;
> + assigned-clock-rates = <786432000>, <722534400>;
> +};
> +
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec1>;
> + phy-handle = <ðphy0>;
> + phy-mode = "rgmii-id";
I believe PHY mode should just be rgmii.
> + phy-supply = <®_ethphy>;
> + fsl,magic-packet;
> + fsl,rgmii_rxc_dly;
> + fsl,rgmii_txc_dly;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy at 7 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + interrupt-parent = <&gpio1>;
> + interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
> + reg = <7>;
> + micrel,led-mode = <0>;
> + };
> + };
> +};
> +
I will add some comments about what exactly below I2C buses are.
> +&i2c1 {
> + clock-frequency = <400000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +
> + pmic at 4b {
> + compatible = "rohm,bd71847";
> + reg = <0x4b>;
> + pinctrl-0 = <&pinctrl_pmic>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <3 GPIO_ACTIVE_LOW>;
> + rohm,reset-snvs-powered;
> +
> + regulators {
> + buck1_reg: BUCK1 {
> + regulator-name = "BUCK1";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <1250>;
> + };
> +
> + buck2_reg: BUCK2 {
> + regulator-name = "BUCK2";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <1250>;
> + rohm,dvs-run-voltage = <1000000>;
> + rohm,dvs-idle-voltage = <900000>;
> + };
> +
> + buck3_reg: BUCK3 {
> + // BUCK5 in datasheet
> + regulator-name = "BUCK3";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + buck4_reg: BUCK4 {
> + // BUCK6 in datasheet
> + regulator-name = "BUCK4";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + buck5_reg: BUCK5 {
> + // BUCK7 in datasheet
> + regulator-name = "BUCK5";
> + regulator-min-microvolt = <1605000>;
> + regulator-max-microvolt = <1995000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + buck6_reg: BUCK6 {
> + // BUCK8 in datasheet
> + regulator-name = "BUCK6";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1400000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo1_reg: LDO1 {
> + regulator-name = "LDO1";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo2_reg: LDO2 {
> + regulator-name = "LDO2";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo3_reg: LDO3 {
> + regulator-name = "LDO3";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo4_reg: LDO4 {
> + regulator-name = "LDO4";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo5_reg: regulator at 12 {
> + reg = <12>;
> + regulator-compatible = "LDO5";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + ldo6_reg: LDO6 {
> + regulator-name = "LDO6";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> + };
> + };
> +
> + /* Epson RX8130 real time clock on carrier board */
> + rtc: rx8130 at 32 {
Node names should be more generic e.g. just rtc and the label is not
required.
> + compatible = "epson,rx8130";
> + reg = <0x32>;
> + };
> +
> + adc: max11607 at 34 {
Dito.
> + compatible = "maxim,max11607";
> + reg = <0x34>;
> + vcc-supply = <&ldo5_reg>;
> + };
> +
> + eeprom at 50 {
Bonus for good node name (;-p).
> + compatible = "st,24c02";
> + pagesize = <16>;
> + reg = <0x50>;
> + };
> +};
> +
> +&i2c2 {
> + clock-frequency = <400000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +};
> +
> +&i2c3 {
> + clock-frequency = <400000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + status = "okay";
> +};
> +
> +&i2c4 {
> + clock-frequency = <400000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c4>;
> + status = "okay";
> +
> + gpio_expander_21: gpio-expander at 21 {
> + compatible = "nxp,pcal6416";
> + gpio-controller;
> + #gpio-cells = <2>;
> + reg = <0x21>;
> + };
> +
> + /* Current measurement into module VCC */
> + ina219 at 40 {
This is just a hwmon.
> + compatible = "ti,ina219";
> + reg = <0x40>;
> + shunt-resistor = <10000>;
> + status = "okay";
> + };
> +
> + /* EEPROM on MIPI-DSI to HDMI adapter */
> + eeprom_50: eeprom at 50 {
> + compatible = "st,24c02";
> + pagesize = <16>;
> + reg = <0x50>;
> + };
> +
> + /* EEPROM on Verdin Development board */
> + eeprom_57: eeprom at 57 {
> + compatible = "st,24c02";
> + pagesize = <16>;
> + reg = <0x57>;
> + };
> +};
> +
> +&snvs_pwrkey {
> + status = "okay";
> +};
> +
> +/* Verdin UART3 */
I believe according to Verdin spec we use underscores for instance
separation e.g. UART_3.
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + fsl,uart-has-rtscts;
> + status = "okay";
> +};
> +
> +/* Verdin UART1 */
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + fsl,uart-has-rtscts;
> + status = "okay";
> +};
> +
> +/* Verdin UART2 */
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + fsl,uart-has-rtscts;
> + status = "okay";
> +};
> +
> +/* On-module eMMC */
> +&usdhc1 {
> + bus-width = <8>;
> + keep-power-in-suspend;
> + non-removable;
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> + pm-ignore-notify;
> + status = "okay";
> + /* TODO Strobe */
> +};
> +
> +/* Verdin SDIO 1 */
Dito e.g. SD_1.
> +&usdhc2 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
> + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
> + bus-width = <4>;
> + vmmc-supply = <®_usdhc2_vmmc>;
> + status = "okay";
> +};
> +
USB comes before USDHC.
> +&usbotg1 {
> + dr_mode = "peripheral";
> + picophy,pre-emp-curr-control = <3>;
> + picophy,dc-vol-level-adjust = <7>;
> + vbus-supply = <®_usb_otg1_vbus>;
> + status = "okay";
> +};
> +
> +&usbotg2 {
> + dr_mode = "host";
> + picophy,pre-emp-curr-control = <3>;
> + picophy,dc-vol-level-adjust = <7>;
> + vbus-supply = <®_usb_otg2_vbus>;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + fsl,ext-reset-output;
> + status = "okay";
> +};
> +
> +&iomuxc {
That muxing had still some issues and got reworked. I will update it in
a v2.
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
> <&pinctrl_gpio3>,
> + <&pinctrl_gpio4>, <&pinctrl_gpio5>,
> <&pinctrl_gpio6>,
> + <&pinctrl_gpio7>, <&pinctrl_gpio8>,
> <&pinctrl_se050_ena>;
> +
> + imx8mm-verdin {
> + pinctrl_ctrl_force_off_moci: forceoffgrp {
> + fsl,pins = <
> + /* SODIMM 250 */
> + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4
> + >;
> + };
> +
> + pinctrl_can1_int: can1intgrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x1c4
> + >;
> + };
> +
> + pinctrl_can2_int: can2intgrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x1c4
> + >;
> + };
> +
> + pinctrl_ecspi2: ecspi2grp {
> + fsl,pins = <
> + /* SODIMM 196 */
> + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK
> 0x4
> + /* SODIMM 200 */
> + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI
> 0x4
> + /* SODIMM 198 */
> + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO
> 0x1c4
> + /* SODIMM 202 */
> + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13
> 0x1c4
> + >;
> + };
> +
> + pinctrl_ecspi3: ecspi3grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK
> 0x4
> + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI
> 0x4
> + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO
> 0x1c4
> + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4
> + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c4
> + >;
> + };
> +
> + pinctrl_fec1: fec1grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC
> 0x3
> + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
> + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3
> 0x1f
> + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2
> 0x1f
> + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1
> 0x1f
> + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0
> 0x1f
> + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3
> 0x91
> + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2
> 0x91
> + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1
> 0x91
> + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0
> 0x91
> + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC
> 0x1f
> + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC
> 0x91
> + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX
> _CTL 0x91
> + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX
> _CTL 0x1f
> + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10
> 0x1c4
> + >;
> + };
> +
> + pinctrl_flexspi0: flexspi0grp {
> + fsl,pins = <
> + /* SODIMM 52 */
> + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
> + /* SODIMM 54 */
> + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B
> 0x82
> + /* SODIMM 64 */
> + MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B
> 0x82
> + /* SODIMM 66 */
> + MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82
> + /* SODIMM 56 */
> + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0
> 0x82
> + /* SODIMM 58 */
> + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1
> 0x82
> + /* SODIMM 60 */
> + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2
> 0x82
> + /* SODIMM 62 */
> + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3
> 0x82
> + >;
> + };
> +
> + /*
> + * (MEZ_)DSI_1_INT# shared with (MEZ_)GPIO_1 on
> + * Verdin Development Board
> + */
> + pinctrl_gpio_hpd: gpiohpdgrp {
> + fsl,pins = <
> + /* SODIMM 17 */
> + MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x184
> + >;
> + };
> +
> + /*
> + * (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on
> + * Verdin Development Board
> + */
> + pinctrl_gpio1: gpio1grp {
> + fsl,pins = <
> + /* SODIMM 206 */
> + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184
> + >;
> + };
> +
> + pinctrl_gpio2: gpio2grp {
> + fsl,pins = <
> + /* SODIMM 208 */
> + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5
> 0x184
> + >;
> + };
> +
> + pinctrl_gpio3: gpio3grp {
> + fsl,pins = <
> + /* SODIMM 210 */
> + MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x184
> + >;
> + };
> +
> + pinctrl_gpio4: gpio4grp {
> + fsl,pins = <
> + /* SODIMM 212 */
> + MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x184
> + >;
> + };
> +
> + pinctrl_gpio5: gpio5grp {
> + fsl,pins = <
> + /* SODIMM 216 */
> + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x184
> + >;
> + };
> +
> + pinctrl_gpio6: gpio6grp {
> + fsl,pins = <
> + /* SODIMM 218 */
> + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11
> 0x184
> + >;
> + };
> +
> + pinctrl_gpio7: gpio7grp {
> + fsl,pins = <
> + /* SODIMM 220 */
> + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x184
> + >;
> + };
> +
> + pinctrl_gpio8: gpio8grp {
> + fsl,pins = <
> + /* SODIMM 222 */
> + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184
> + >;
> + };
> +
> + /* On Module I2C */
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400
> 001c6
> + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400
> 001c6
> + >;
> + };
> +
> + /* Verdin I2C_4_CSI */
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + /* SODIMM 55 */
> + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400
> 001c6
> + /* SODIMM 53 */
> + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400
> 001c6
> + >;
> + };
> +
> + /* Verdin I2C_2_DSI */
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + /* SODIMM 95 */
> + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400
> 001c6
> + /* SODIMM 93 */
> + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400
> 001c6
> + >;
> + };
> +
> + /* Verdin I2C_1 */
> + pinctrl_i2c4: i2c4grp {
> + fsl,pins = <
> + /* SODIMM 14 */
> + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400
> 001c6
> + /* SODIMM 12 */
> + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400
> 001c6
> + >;
> + };
> +
> + pinctrl_pcie0: pcie0grp {
> + fsl,pins = <
> + /* SODIMM 244 */
> + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6
> + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19
> 0x6
> + >;
> + };
> +
> + pinctrl_pmic: pmicirq {
> + fsl,pins = <
> + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
> + >;
> + };
> +
> + pinctrl_reg_eth: regethgrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20
> 0x184
> + >;
> + };
> +
> + pinctrl_sai2: sai2grp {
> + fsl,pins = <
> + /* SODIMM 32 */
> + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC
> 0xd6
> + /* SODIMM 30 */
> + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK
> 0xd6
> + /* SODIMM 38 */
> + MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
> + /* SODIMM 36 */
> + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0
> 0xd6
> + /* SODIMM 34 */
> + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0
> 0xd6
> + >;
> + };
> +
> + pinctrl_sai5: sai5grp {
> + fsl,pins = <
> + /* SODIMM 48 */
> + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0
> 0xd6
> + /* SODIMM 44 */
> + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC
> 0xd6
> + /* SODIMM 42 */
> + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK
> 0xd6
> + /* SODIMM 46 */
> + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0
> 0xd6
> + >;
> + };
> +
> + pinctrl_se050_ena: se050enagrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x184
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + /* SODIMM 149 */
> + MX8MM_IOMUXC_SAI2_RXFS_UART1_TX
> 0x1c4
> + /* SODIMM 147 */
> + MX8MM_IOMUXC_SAI2_RXC_UART1_RX
> 0x1c4
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + /* SODIMM 129 */
> + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX
> 0x1c4
> + /* SODIMM 131 */
> + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX
> 0x1c4
> + /* SODIMM 133 */
> + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B
> 0x1c4
> + /* SODIMM 135 */
> + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B
> 0x1c4
> + >;
> + };
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <
> + /* SODIMM 137 */
> + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX
> 0x1c4
> + /* SODIMM 139 */
> + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX
> 0x1c4
> + /* SODIMM 141 */
> + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_
> B 0x1c4
> + /* SODIMM 143 */
> + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B
> 0x1c4
> + >;
> + };
> +
> + pinctrl_uart4: uart4grp {
> + fsl,pins = <
> + /* SODIMM 151 */
> + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX
> 0x1c4
> + /* SODIMM 153 */
> + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX
> 0x1c4
> + >;
> + };
> +
> + pinctrl_reg_usb1_en: regusb1en {
> + fsl,pins = <
> + /* SODIMM 155 */
> + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12
> 0x184
> + >;
> + };
> +
> + pinctrl_reg_usb2_en: regusb2en {
> + fsl,pins = <
> + /* SODIMM 185 */
> + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14
> 0x184
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
> 0x190
> + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
> 0x1d0
> + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
> 0x1d0
> + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
> 0x1d0
> + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
> 0x1d0
> + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
> 0x1d0
> + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4
> 0x1d0
> + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5
> 0x1d0
> + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6
> 0x1d0
> + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7
> 0x1d0
> + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE
> 0x190
> + >;
> + };
> +
> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
> 0x194
> + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
> 0x1d4
> + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
> 0x1d4
> + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
> 0x1d4
> + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
> 0x1d4
> + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
> 0x1d4
> + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4
> 0x1d4
> + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5
> 0x1d4
> + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6
> 0x1d4
> + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7
> 0x1d4
> + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE
> 0x194
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
> 0x196
> + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
> 0x1d6
> + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
> 0x1d6
> + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
> 0x1d6
> + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
> 0x1d6
> + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
> 0x1d6
> + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4
> 0x1d6
> + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5
> 0x1d6
> + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6
> 0x1d6
> + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7
> 0x1d6
> + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE
> 0x196
> + >;
> + };
> +
> + pinctrl_usdhc2_cd: usdhc2cdgrp {
> + fsl,pins = <
> + /* SODIMM 84 */
> + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
> + >;
> + };
> +
> + pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
> + fsl,pins = <
> + /* SODIMM 76 */
> + MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x184
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + /* SODIMM 78 */
> + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK
> 0x190
> + /* SODIMM 74 */
> + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD
> 0x1d0
> + /* SODIMM 80 */
> + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0
> 0x1d0
> + /* SODIMM 82 */
> + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1
> 0x1d0
> + /* SODIMM 70 */
> + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2
> 0x1d0
> + /* SODIMM 72 */
> + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3
> 0x1d0
> + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT
> 0x1d0
> + >;
> + };
> +
> + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
> + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
> + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0
> 0x1d4
> + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1
> 0x1d4
> + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2
> 0x1d4
> + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3
> 0x1d4
> + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT
> 0x1d0
> + >;
> + };
> +
> + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
> + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
> + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0
> 0x1d6
> + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1
> 0x1d6
> + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2
> 0x1d6
> + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3
> 0x1d6
> + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT
> 0x1d0
> + >;
> + };
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
> + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
> + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0
> 0x1d0
> + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1
> 0x1d0
> + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2
> 0x1d0
> + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3
> 0x1d0
> + >;
> + };
> +
> + pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> + fsl,pins = <
> + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
> + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
> + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0
> 0x1d4
> + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1
> 0x1d4
> + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2
> 0x1d4
> + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3
> 0x1d4
> + >;
> + };
> +
> + pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> + fsl,pins = <
> + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
> + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
> + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0
> 0x1d6
> + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1
> 0x1d6
> + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2
> 0x1d6
> + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3
> 0x1d6
> + >;
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B
> 0xc6
> + >;
> + };
> +
> + pinctrl_wifi_ctrl: wifictrlgrp {
> + fsl,pins = <
> + /* WIFI_WKUP_BT */
> + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16
> 0x1c4
> + /* WIFI_WKUP_WLAN */
> + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10
> 0x1c4
> + /* WIFI_W_WKUP_HOST */
> + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4
> + >;
> + };
> +
> + pinctrl_wifi_pwr_en: wifipwrengrp {
> + fsl,pins = <
> + /* PMIC_EN_WIFI */
> + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x184
> + >;
> + };
> +
> + pinctrl_wifi_i2s: wifii2sgrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK
> 0xd6
> + MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0
> 0xd6
> + MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC
> 0xd6
> + MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0
> 0xd6
> + >;
> + };
> + };
> +};
> diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-
> imx/imx8m/Kconfig
> index 72affb1bdc..58f1758ab6 100644
> --- a/arch/arm/mach-imx/imx8m/Kconfig
> +++ b/arch/arm/mach-imx/imx8m/Kconfig
> @@ -50,11 +50,18 @@ config TARGET_IMX8MP_EVK
> select SUPPORT_SPL
> select IMX8M_LPDDR4
>
> +config TARGET_VERDIN_IMX8MM
> + bool "Support Toradex Verdin iMX8M Mini module"
> + select IMX8MM
> + select SUPPORT_SPL
> + select IMX8M_LPDDR4
> +
> endchoice
>
> source "board/freescale/imx8mq_evk/Kconfig"
> source "board/freescale/imx8mm_evk/Kconfig"
> source "board/freescale/imx8mn_evk/Kconfig"
> source "board/freescale/imx8mp_evk/Kconfig"
> +source "board/toradex/verdin-imx8mm/Kconfig"
>
> endif
> diff --git a/board/toradex/verdin-imx8mm/Kconfig
> b/board/toradex/verdin-imx8mm/Kconfig
> new file mode 100644
> index 0000000000..8a2fe98682
> --- /dev/null
> +++ b/board/toradex/verdin-imx8mm/Kconfig
> @@ -0,0 +1,30 @@
> +if TARGET_VERDIN_IMX8MM
> +
> +config SYS_BOARD
> + default "verdin-imx8mm"
> +
> +config SYS_VENDOR
> + default "toradex"
> +
> +config SYS_CONFIG_NAME
> + default "verdin-imx8mm"
> +
> +config TDX_CFG_BLOCK
> + default y
> +
> +config TDX_HAVE_MMC
> + default y
> +
> +config TDX_CFG_BLOCK_DEV
> + default "0"
> +
> +config TDX_CFG_BLOCK_PART
> + default "1"
> +
> +# Toradex config block in eMMC, at the end of 1st "boot sector"
> +config TDX_CFG_BLOCK_OFFSET
> + default "-512"
> +
> +source "board/toradex/common/Kconfig"
> +
> +endif
> diff --git a/board/toradex/verdin-imx8mm/Makefile
> b/board/toradex/verdin-imx8mm/Makefile
> new file mode 100644
> index 0000000000..7161b19d0f
> --- /dev/null
> +++ b/board/toradex/verdin-imx8mm/Makefile
> @@ -0,0 +1,12 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright 2018-2019 Toradex
> +#
> +
> +obj-y += verdin-imx8mm.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
> +obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
I don't think any DDR4 aka non-LPDDR stuff exists for Verdin.
> +endif
> diff --git a/board/toradex/verdin-imx8mm/imximage.cfg
> b/board/toradex/verdin-imx8mm/imximage.cfg
> new file mode 100644
> index 0000000000..ce00628c14
> --- /dev/null
> +++ b/board/toradex/verdin-imx8mm/imximage.cfg
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2019 Toradex AG
> + */
> +
> +#define __ASSEMBLY__
> +
> +FIT
> +BOOT_FROM emmc_fastboot
> +LOADER spl/u-boot-spl-ddr.bin 0x7E1000
> +SECOND_LOADER u-boot.itb 0x40200000 0x60000
> +
> +DDR_FW lpddr4_pmu_train_1d_imem.bin
> +DDR_FW lpddr4_pmu_train_1d_dmem.bin
> +DDR_FW lpddr4_pmu_train_2d_imem.bin
> +DDR_FW lpddr4_pmu_train_2d_dmem.bin
> diff --git a/board/toradex/verdin-imx8mm/lpddr4_timing.c
> b/board/toradex/verdin-imx8mm/lpddr4_timing.c
> new file mode 100644
> index 0000000000..5584c28047
> --- /dev/null
> +++ b/board/toradex/verdin-imx8mm/lpddr4_timing.c
> @@ -0,0 +1,1851 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 Toradex AG
> + *
> + * Generated code from MX8M_DDR_tool
> + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
> + *
> + * DDR calibration created with mscale_ddr_tool_v210_setup.exe using
> + * MX8M_Mini_LPDDR4_RPA_v14 Verdin iMX8MM V1.0.xlsx as of 1. Nov.
> 2019.
> + */
> +
> +#include <linux/kernel.h>
> +#include <asm/arch/ddr.h>
> +
> +struct dram_cfg_param ddr_ddrc_cfg[] = {
> + /** Initialize DDRC registers **/
> + {0x3d400304, 0x1},
> + {0x3d400030, 0x1},
> + {0x3d400000, 0xa1080020},
> + {0x3d400020, 0x203},
> + {0x3d400024, 0x3a980},
> + {0x3d400064, 0x5b00d2},
> + {0x3d4000d0, 0xc00305ba},
> + {0x3d4000d4, 0x940000},
> + {0x3d4000dc, 0xd4002d},
> + {0x3d4000e0, 0x310000},
> + {0x3d4000e8, 0x66004d},
> + {0x3d4000ec, 0x16004d},
> + {0x3d400100, 0x191e1920},
> + {0x3d400104, 0x60630},
> + {0x3d40010c, 0xb0b000},
> + {0x3d400110, 0xe04080e},
> + {0x3d400114, 0x2040c0c},
> + {0x3d400118, 0x1010007},
> + {0x3d40011c, 0x401},
> + {0x3d400130, 0x20600},
> + {0x3d400134, 0xc100002},
> + {0x3d400138, 0xd8},
> + {0x3d400144, 0x96004b},
> + {0x3d400180, 0x2ee0017},
> + {0x3d400184, 0x2605b8e},
> + {0x3d400188, 0x0},
> + {0x3d400190, 0x497820a},
> + {0x3d400194, 0x80303},
> + {0x3d4001b4, 0x170a},
> + {0x3d4001a0, 0xe0400018},
> + {0x3d4001a4, 0xdf00e4},
> + {0x3d4001a8, 0x80000000},
> + {0x3d4001b0, 0x11},
> + {0x3d4001c0, 0x1},
> + {0x3d4001c4, 0x1},
> + {0x3d4000f4, 0xc99},
> + {0x3d400108, 0x70e1617},
> + {0x3d400200, 0x1f},
> + {0x3d40020c, 0x0},
> + {0x3d400210, 0x1f1f},
> + {0x3d400204, 0x80808},
> + {0x3d400214, 0x7070707},
> + {0x3d400218, 0x7070707},
> + {0x3d400250, 0x29001701},
> + {0x3d400254, 0x2c},
> + {0x3d40025c, 0x4000030},
> + {0x3d400264, 0x900093e7},
> + {0x3d40026c, 0x2005574},
> + {0x3d400400, 0x111},
> + {0x3d400408, 0x72ff},
> + {0x3d400494, 0x2100e07},
> + {0x3d400498, 0x620096},
> + {0x3d40049c, 0x1100e07},
> + {0x3d4004a0, 0xc8012c},
> + {0x3d402020, 0x1},
> + {0x3d402024, 0x7d00},
> + {0x3d402050, 0x20d040},
> + {0x3d402064, 0xc001c},
> + {0x3d4020dc, 0x840000},
> + {0x3d4020e0, 0x310000},
> + {0x3d4020e8, 0x66004d},
> + {0x3d4020ec, 0x16004d},
> + {0x3d402100, 0xa040305},
> + {0x3d402104, 0x30407},
> + {0x3d402108, 0x203060b},
> + {0x3d40210c, 0x505000},
> + {0x3d402110, 0x2040202},
> + {0x3d402114, 0x2030202},
> + {0x3d402118, 0x1010004},
> + {0x3d40211c, 0x301},
> + {0x3d402130, 0x20300},
> + {0x3d402134, 0xa100002},
> + {0x3d402138, 0x1d},
> + {0x3d402144, 0x14000a},
> + {0x3d402180, 0x640004},
> + {0x3d402190, 0x3818200},
> + {0x3d402194, 0x80303},
> + {0x3d4021b4, 0x100},
> + {0x3d4020f4, 0xc99},
> + {0x3d403020, 0x1},
> + {0x3d403024, 0x1f40},
> + {0x3d403050, 0x20d040},
> + {0x3d403064, 0x30007},
> + {0x3d4030dc, 0x840000},
> + {0x3d4030e0, 0x310000},
> + {0x3d4030e8, 0x66004d},
> + {0x3d4030ec, 0x16004d},
> + {0x3d403100, 0xa010102},
> + {0x3d403104, 0x30404},
> + {0x3d403108, 0x203060b},
> + {0x3d40310c, 0x505000},
> + {0x3d403110, 0x2040202},
> + {0x3d403114, 0x2030202},
> + {0x3d403118, 0x1010004},
> + {0x3d40311c, 0x301},
> + {0x3d403130, 0x20300},
> + {0x3d403134, 0xa100002},
> + {0x3d403138, 0x8},
> + {0x3d403144, 0x50003},
> + {0x3d403180, 0x190004},
> + {0x3d403190, 0x3818200},
> + {0x3d403194, 0x80303},
> + {0x3d4031b4, 0x100},
> + {0x3d4030f4, 0xc99},
> + {0x3d400028, 0x0},
> +};
> +
> +/* PHY Initialize Configuration */
> +struct dram_cfg_param ddr_ddrphy_cfg[] = {
> + {0x100a0, 0x0},
> + {0x100a1, 0x1},
> + {0x100a2, 0x2},
> + {0x100a3, 0x3},
> + {0x100a4, 0x4},
> + {0x100a5, 0x5},
> + {0x100a6, 0x6},
> + {0x100a7, 0x7},
> + {0x110a0, 0x0},
> + {0x110a1, 0x1},
> + {0x110a2, 0x3},
> + {0x110a3, 0x4},
> + {0x110a4, 0x5},
> + {0x110a5, 0x2},
> + {0x110a6, 0x6},
> + {0x110a7, 0x7},
> + {0x120a0, 0x0},
> + {0x120a1, 0x1},
> + {0x120a2, 0x3},
> + {0x120a3, 0x4},
> + {0x120a4, 0x5},
> + {0x120a5, 0x2},
> + {0x120a6, 0x6},
> + {0x120a7, 0x7},
> + {0x130a0, 0x0},
> + {0x130a1, 0x1},
> + {0x130a2, 0x2},
> + {0x130a3, 0x3},
> + {0x130a4, 0x4},
> + {0x130a5, 0x5},
> + {0x130a6, 0x6},
> + {0x130a7, 0x7},
> + {0x1005f, 0x1ff},
> + {0x1015f, 0x1ff},
> + {0x1105f, 0x1ff},
> + {0x1115f, 0x1ff},
> + {0x1205f, 0x1ff},
> + {0x1215f, 0x1ff},
> + {0x1305f, 0x1ff},
> + {0x1315f, 0x1ff},
> + {0x11005f, 0x1ff},
> + {0x11015f, 0x1ff},
> + {0x11105f, 0x1ff},
> + {0x11115f, 0x1ff},
> + {0x11205f, 0x1ff},
> + {0x11215f, 0x1ff},
> + {0x11305f, 0x1ff},
> + {0x11315f, 0x1ff},
> + {0x21005f, 0x1ff},
> + {0x21015f, 0x1ff},
> + {0x21105f, 0x1ff},
> + {0x21115f, 0x1ff},
> + {0x21205f, 0x1ff},
> + {0x21215f, 0x1ff},
> + {0x21305f, 0x1ff},
> + {0x21315f, 0x1ff},
> + {0x55, 0x1ff},
> + {0x1055, 0x1ff},
> + {0x2055, 0x1ff},
> + {0x3055, 0x1ff},
> + {0x4055, 0x1ff},
> + {0x5055, 0x1ff},
> + {0x6055, 0x1ff},
> + {0x7055, 0x1ff},
> + {0x8055, 0x1ff},
> + {0x9055, 0x1ff},
> + {0x200c5, 0x19},
> + {0x1200c5, 0x7},
> + {0x2200c5, 0x7},
> + {0x2002e, 0x2},
> + {0x12002e, 0x2},
> + {0x22002e, 0x2},
> + {0x90204, 0x0},
> + {0x190204, 0x0},
> + {0x290204, 0x0},
> + {0x20024, 0x1ab},
> + {0x2003a, 0x0},
> + {0x120024, 0x1ab},
> + {0x2003a, 0x0},
> + {0x220024, 0x1ab},
> + {0x2003a, 0x0},
> + {0x20056, 0x3},
> + {0x120056, 0xa},
> + {0x220056, 0xa},
> + {0x1004d, 0xe00},
> + {0x1014d, 0xe00},
> + {0x1104d, 0xe00},
> + {0x1114d, 0xe00},
> + {0x1204d, 0xe00},
> + {0x1214d, 0xe00},
> + {0x1304d, 0xe00},
> + {0x1314d, 0xe00},
> + {0x11004d, 0xe00},
> + {0x11014d, 0xe00},
> + {0x11104d, 0xe00},
> + {0x11114d, 0xe00},
> + {0x11204d, 0xe00},
> + {0x11214d, 0xe00},
> + {0x11304d, 0xe00},
> + {0x11314d, 0xe00},
> + {0x21004d, 0xe00},
> + {0x21014d, 0xe00},
> + {0x21104d, 0xe00},
> + {0x21114d, 0xe00},
> + {0x21204d, 0xe00},
> + {0x21214d, 0xe00},
> + {0x21304d, 0xe00},
> + {0x21314d, 0xe00},
> + {0x10049, 0xeba},
> + {0x10149, 0xeba},
> + {0x11049, 0xeba},
> + {0x11149, 0xeba},
> + {0x12049, 0xeba},
> + {0x12149, 0xeba},
> + {0x13049, 0xeba},
> + {0x13149, 0xeba},
> + {0x110049, 0xeba},
> + {0x110149, 0xeba},
> + {0x111049, 0xeba},
> + {0x111149, 0xeba},
> + {0x112049, 0xeba},
> + {0x112149, 0xeba},
> + {0x113049, 0xeba},
> + {0x113149, 0xeba},
> + {0x210049, 0xeba},
> + {0x210149, 0xeba},
> + {0x211049, 0xeba},
> + {0x211149, 0xeba},
> + {0x212049, 0xeba},
> + {0x212149, 0xeba},
> + {0x213049, 0xeba},
> + {0x213149, 0xeba},
> + {0x43, 0x63},
> + {0x1043, 0x63},
> + {0x2043, 0x63},
> + {0x3043, 0x63},
> + {0x4043, 0x63},
> + {0x5043, 0x63},
> + {0x6043, 0x63},
> + {0x7043, 0x63},
> + {0x8043, 0x63},
> + {0x9043, 0x63},
> + {0x20018, 0x3},
> + {0x20075, 0x4},
> + {0x20050, 0x0},
> + {0x20008, 0x2ee},
> + {0x120008, 0x64},
> + {0x220008, 0x19},
> + {0x20088, 0x9},
> + {0x200b2, 0xdc},
> + {0x10043, 0x5a1},
> + {0x10143, 0x5a1},
> + {0x11043, 0x5a1},
> + {0x11143, 0x5a1},
> + {0x12043, 0x5a1},
> + {0x12143, 0x5a1},
> + {0x13043, 0x5a1},
> + {0x13143, 0x5a1},
> + {0x1200b2, 0xdc},
> + {0x110043, 0x5a1},
> + {0x110143, 0x5a1},
> + {0x111043, 0x5a1},
> + {0x111143, 0x5a1},
> + {0x112043, 0x5a1},
> + {0x112143, 0x5a1},
> + {0x113043, 0x5a1},
> + {0x113143, 0x5a1},
> + {0x2200b2, 0xdc},
> + {0x210043, 0x5a1},
> + {0x210143, 0x5a1},
> + {0x211043, 0x5a1},
> + {0x211143, 0x5a1},
> + {0x212043, 0x5a1},
> + {0x212143, 0x5a1},
> + {0x213043, 0x5a1},
> + {0x213143, 0x5a1},
> + {0x200fa, 0x1},
> + {0x1200fa, 0x1},
> + {0x2200fa, 0x1},
> + {0x20019, 0x1},
> + {0x120019, 0x1},
> + {0x220019, 0x1},
> + {0x200f0, 0x660},
> + {0x200f1, 0x0},
> + {0x200f2, 0x4444},
> + {0x200f3, 0x8888},
> + {0x200f4, 0x5665},
> + {0x200f5, 0x0},
> + {0x200f6, 0x0},
> + {0x200f7, 0xf000},
> + {0x20025, 0x0},
> + {0x2002d, 0x0},
> + {0x12002d, 0x0},
> + {0x22002d, 0x0},
> + {0x200c7, 0x21},
> + {0x1200c7, 0x21},
> + {0x2200c7, 0x21},
> + {0x200ca, 0x24},
> + {0x1200ca, 0x24},
> + {0x2200ca, 0x24},
> +};
> +
> +/* ddr phy trained csr */
> +struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
> + { 0x200b2, 0x0 },
> + { 0x1200b2, 0x0 },
> + { 0x2200b2, 0x0 },
> + { 0x200cb, 0x0 },
> + { 0x10043, 0x0 },
> + { 0x110043, 0x0 },
> + { 0x210043, 0x0 },
> + { 0x10143, 0x0 },
> + { 0x110143, 0x0 },
> + { 0x210143, 0x0 },
> + { 0x11043, 0x0 },
> + { 0x111043, 0x0 },
> + { 0x211043, 0x0 },
> + { 0x11143, 0x0 },
> + { 0x111143, 0x0 },
> + { 0x211143, 0x0 },
> + { 0x12043, 0x0 },
> + { 0x112043, 0x0 },
> + { 0x212043, 0x0 },
> + { 0x12143, 0x0 },
> + { 0x112143, 0x0 },
> + { 0x212143, 0x0 },
> + { 0x13043, 0x0 },
> + { 0x113043, 0x0 },
> + { 0x213043, 0x0 },
> + { 0x13143, 0x0 },
> + { 0x113143, 0x0 },
> + { 0x213143, 0x0 },
> + { 0x80, 0x0 },
> + { 0x100080, 0x0 },
> + { 0x200080, 0x0 },
> + { 0x1080, 0x0 },
> + { 0x101080, 0x0 },
> + { 0x201080, 0x0 },
> + { 0x2080, 0x0 },
> + { 0x102080, 0x0 },
> + { 0x202080, 0x0 },
> + { 0x3080, 0x0 },
> + { 0x103080, 0x0 },
> + { 0x203080, 0x0 },
> + { 0x4080, 0x0 },
> + { 0x104080, 0x0 },
> + { 0x204080, 0x0 },
> + { 0x5080, 0x0 },
> + { 0x105080, 0x0 },
> + { 0x205080, 0x0 },
> + { 0x6080, 0x0 },
> + { 0x106080, 0x0 },
> + { 0x206080, 0x0 },
> + { 0x7080, 0x0 },
> + { 0x107080, 0x0 },
> + { 0x207080, 0x0 },
> + { 0x8080, 0x0 },
> + { 0x108080, 0x0 },
> + { 0x208080, 0x0 },
> + { 0x9080, 0x0 },
> + { 0x109080, 0x0 },
> + { 0x209080, 0x0 },
> + { 0x10080, 0x0 },
> + { 0x110080, 0x0 },
> + { 0x210080, 0x0 },
> + { 0x10180, 0x0 },
> + { 0x110180, 0x0 },
> + { 0x210180, 0x0 },
> + { 0x11080, 0x0 },
> + { 0x111080, 0x0 },
> + { 0x211080, 0x0 },
> + { 0x11180, 0x0 },
> + { 0x111180, 0x0 },
> + { 0x211180, 0x0 },
> + { 0x12080, 0x0 },
> + { 0x112080, 0x0 },
> + { 0x212080, 0x0 },
> + { 0x12180, 0x0 },
> + { 0x112180, 0x0 },
> + { 0x212180, 0x0 },
> + { 0x13080, 0x0 },
> + { 0x113080, 0x0 },
> + { 0x213080, 0x0 },
> + { 0x13180, 0x0 },
> + { 0x113180, 0x0 },
> + { 0x213180, 0x0 },
> + { 0x10081, 0x0 },
> + { 0x110081, 0x0 },
> + { 0x210081, 0x0 },
> + { 0x10181, 0x0 },
> + { 0x110181, 0x0 },
> + { 0x210181, 0x0 },
> + { 0x11081, 0x0 },
> + { 0x111081, 0x0 },
> + { 0x211081, 0x0 },
> + { 0x11181, 0x0 },
> + { 0x111181, 0x0 },
> + { 0x211181, 0x0 },
> + { 0x12081, 0x0 },
> + { 0x112081, 0x0 },
> + { 0x212081, 0x0 },
> + { 0x12181, 0x0 },
> + { 0x112181, 0x0 },
> + { 0x212181, 0x0 },
> + { 0x13081, 0x0 },
> + { 0x113081, 0x0 },
> + { 0x213081, 0x0 },
> + { 0x13181, 0x0 },
> + { 0x113181, 0x0 },
> + { 0x213181, 0x0 },
> + { 0x100d0, 0x0 },
> + { 0x1100d0, 0x0 },
> + { 0x2100d0, 0x0 },
> + { 0x101d0, 0x0 },
> + { 0x1101d0, 0x0 },
> + { 0x2101d0, 0x0 },
> + { 0x110d0, 0x0 },
> + { 0x1110d0, 0x0 },
> + { 0x2110d0, 0x0 },
> + { 0x111d0, 0x0 },
> + { 0x1111d0, 0x0 },
> + { 0x2111d0, 0x0 },
> + { 0x120d0, 0x0 },
> + { 0x1120d0, 0x0 },
> + { 0x2120d0, 0x0 },
> + { 0x121d0, 0x0 },
> + { 0x1121d0, 0x0 },
> + { 0x2121d0, 0x0 },
> + { 0x130d0, 0x0 },
> + { 0x1130d0, 0x0 },
> + { 0x2130d0, 0x0 },
> + { 0x131d0, 0x0 },
> + { 0x1131d0, 0x0 },
> + { 0x2131d0, 0x0 },
> + { 0x100d1, 0x0 },
> + { 0x1100d1, 0x0 },
> + { 0x2100d1, 0x0 },
> + { 0x101d1, 0x0 },
> + { 0x1101d1, 0x0 },
> + { 0x2101d1, 0x0 },
> + { 0x110d1, 0x0 },
> + { 0x1110d1, 0x0 },
> + { 0x2110d1, 0x0 },
> + { 0x111d1, 0x0 },
> + { 0x1111d1, 0x0 },
> + { 0x2111d1, 0x0 },
> + { 0x120d1, 0x0 },
> + { 0x1120d1, 0x0 },
> + { 0x2120d1, 0x0 },
> + { 0x121d1, 0x0 },
> + { 0x1121d1, 0x0 },
> + { 0x2121d1, 0x0 },
> + { 0x130d1, 0x0 },
> + { 0x1130d1, 0x0 },
> + { 0x2130d1, 0x0 },
> + { 0x131d1, 0x0 },
> + { 0x1131d1, 0x0 },
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> + { 0x12830, 0x0 },
> + { 0x13040, 0x0 },
> + { 0x13140, 0x0 },
> + { 0x13240, 0x0 },
> + { 0x13340, 0x0 },
> + { 0x13440, 0x0 },
> + { 0x13540, 0x0 },
> + { 0x13640, 0x0 },
> + { 0x13740, 0x0 },
> + { 0x13840, 0x0 },
> + { 0x13030, 0x0 },
> + { 0x13130, 0x0 },
> + { 0x13230, 0x0 },
> + { 0x13330, 0x0 },
> + { 0x13430, 0x0 },
> + { 0x13530, 0x0 },
> + { 0x13630, 0x0 },
> + { 0x13730, 0x0 },
> + { 0x13830, 0x0 },
> +};
> +
> +/* P0 message block paremeter for training firmware */
> +struct dram_cfg_param ddr_fsp0_cfg[] = {
> + {0xd0000, 0x0},
> + {0x54003, 0xbb8},
> + {0x54004, 0x2},
> + {0x54005, 0x2228},
> + {0x54006, 0x11},
> + {0x54008, 0x131f},
> + {0x54009, 0xc8},
> + {0x5400b, 0x2},
> + {0x5400d, 0x100},
> + {0x54012, 0x110},
> + {0x54019, 0x2dd4},
> + {0x5401a, 0x31},
> + {0x5401b, 0x4d66},
> + {0x5401c, 0x4d00},
> + {0x5401e, 0x16},
> + {0x5401f, 0x2dd4},
> + {0x54020, 0x31},
> + {0x54021, 0x4d66},
> + {0x54022, 0x4d00},
> + {0x54024, 0x16},
> + {0x5402b, 0x1000},
> + {0x5402c, 0x1},
> + {0x54032, 0xd400},
> + {0x54033, 0x312d},
> + {0x54034, 0x6600},
> + {0x54035, 0x4d},
> + {0x54036, 0x4d},
> + {0x54037, 0x1600},
> + {0x54038, 0xd400},
> + {0x54039, 0x312d},
> + {0x5403a, 0x6600},
> + {0x5403b, 0x4d},
> + {0x5403c, 0x4d},
> + {0x5403d, 0x1600},
> + {0xd0000, 0x1},
> +};
> +
> +/* P1 message block paremeter for training firmware */
> +struct dram_cfg_param ddr_fsp1_cfg[] = {
> + {0xd0000, 0x0},
> + {0x54002, 0x101},
> + {0x54003, 0x190},
> + {0x54004, 0x2},
> + {0x54005, 0x2228},
> + {0x54006, 0x11},
> + {0x54008, 0x121f},
> + {0x54009, 0xc8},
> + {0x5400b, 0x2},
> + {0x5400d, 0x100},
> + {0x54012, 0x110},
> + {0x54019, 0x84},
> + {0x5401a, 0x31},
> + {0x5401b, 0x4d66},
> + {0x5401c, 0x4d00},
> + {0x5401e, 0x16},
> + {0x5401f, 0x84},
> + {0x54020, 0x31},
> + {0x54021, 0x4d66},
> + {0x54022, 0x4d00},
> + {0x54024, 0x16},
> + {0x5402b, 0x1000},
> + {0x5402c, 0x1},
> + {0x54032, 0x8400},
> + {0x54033, 0x3100},
> + {0x54034, 0x6600},
> + {0x54035, 0x4d},
> + {0x54036, 0x4d},
> + {0x54037, 0x1600},
> + {0x54038, 0x8400},
> + {0x54039, 0x3100},
> + {0x5403a, 0x6600},
> + {0x5403b, 0x4d},
> + {0x5403c, 0x4d},
> + {0x5403d, 0x1600},
> + {0xd0000, 0x1},
> +};
> +
> +/* P2 message block paremeter for training firmware */
> +struct dram_cfg_param ddr_fsp2_cfg[] = {
> + {0xd0000, 0x0},
> + {0x54002, 0x102},
> + {0x54003, 0x64},
> + {0x54004, 0x2},
> + {0x54005, 0x2228},
> + {0x54006, 0x11},
> + {0x54008, 0x121f},
> + {0x54009, 0xc8},
> + {0x5400b, 0x2},
> + {0x5400d, 0x100},
> + {0x54012, 0x110},
> + {0x54019, 0x84},
> + {0x5401a, 0x31},
> + {0x5401b, 0x4d66},
> + {0x5401c, 0x4d00},
> + {0x5401e, 0x16},
> + {0x5401f, 0x84},
> + {0x54020, 0x31},
> + {0x54021, 0x4d66},
> + {0x54022, 0x4d00},
> + {0x54024, 0x16},
> + {0x5402b, 0x1000},
> + {0x5402c, 0x1},
> + {0x54032, 0x8400},
> + {0x54033, 0x3100},
> + {0x54034, 0x6600},
> + {0x54035, 0x4d},
> + {0x54036, 0x4d},
> + {0x54037, 0x1600},
> + {0x54038, 0x8400},
> + {0x54039, 0x3100},
> + {0x5403a, 0x6600},
> + {0x5403b, 0x4d},
> + {0x5403c, 0x4d},
> + {0x5403d, 0x1600},
> + {0xd0000, 0x1},
> +};
> +
> +/* P0 2D message block paremeter for training firmware */
> +struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
> + {0xd0000, 0x0},
> + {0x54003, 0xbb8},
> + {0x54004, 0x2},
> + {0x54005, 0x2228},
> + {0x54006, 0x11},
> + {0x54008, 0x61},
> + {0x54009, 0xc8},
> + {0x5400b, 0x2},
> + {0x5400f, 0x100},
> + {0x54010, 0x1f7f},
> + {0x54012, 0x110},
> + {0x54019, 0x2dd4},
> + {0x5401a, 0x31},
> + {0x5401b, 0x4d66},
> + {0x5401c, 0x4d00},
> + {0x5401e, 0x16},
> + {0x5401f, 0x2dd4},
> + {0x54020, 0x31},
> + {0x54021, 0x4d66},
> + {0x54022, 0x4d00},
> + {0x54024, 0x16},
> + {0x5402b, 0x1000},
> + {0x5402c, 0x1},
> + {0x54032, 0xd400},
> + {0x54033, 0x312d},
> + {0x54034, 0x6600},
> + {0x54035, 0x4d},
> + {0x54036, 0x4d},
> + {0x54037, 0x1600},
> + {0x54038, 0xd400},
> + {0x54039, 0x312d},
> + {0x5403a, 0x6600},
> + {0x5403b, 0x4d},
> + {0x5403c, 0x4d},
> + {0x5403d, 0x1600},
> + { 0xd0000, 0x1 },
> +};
> +
> +/* DRAM PHY init engine image */
> +struct dram_cfg_param ddr_phy_pie[] = {
> + {0xd0000, 0x0},
> + {0x90000, 0x10},
> + {0x90001, 0x400},
> + {0x90002, 0x10e},
> + {0x90003, 0x0},
> + {0x90004, 0x0},
> + {0x90005, 0x8},
> + {0x90029, 0xb},
> + {0x9002a, 0x480},
> + {0x9002b, 0x109},
> + {0x9002c, 0x8},
> + {0x9002d, 0x448},
> + {0x9002e, 0x139},
> + {0x9002f, 0x8},
> + {0x90030, 0x478},
> + {0x90031, 0x109},
> + {0x90032, 0x0},
> + {0x90033, 0xe8},
> + {0x90034, 0x109},
> + {0x90035, 0x2},
> + {0x90036, 0x10},
> + {0x90037, 0x139},
> + {0x90038, 0xf},
> + {0x90039, 0x7c0},
> + {0x9003a, 0x139},
> + {0x9003b, 0x44},
> + {0x9003c, 0x630},
> + {0x9003d, 0x159},
> + {0x9003e, 0x14f},
> + {0x9003f, 0x630},
> + {0x90040, 0x159},
> + {0x90041, 0x47},
> + {0x90042, 0x630},
> + {0x90043, 0x149},
> + {0x90044, 0x4f},
> + {0x90045, 0x630},
> + {0x90046, 0x179},
> + {0x90047, 0x8},
> + {0x90048, 0xe0},
> + {0x90049, 0x109},
> + {0x9004a, 0x0},
> + {0x9004b, 0x7c8},
> + {0x9004c, 0x109},
> + {0x9004d, 0x0},
> + {0x9004e, 0x1},
> + {0x9004f, 0x8},
> + {0x90050, 0x0},
> + {0x90051, 0x45a},
> + {0x90052, 0x9},
> + {0x90053, 0x0},
> + {0x90054, 0x448},
> + {0x90055, 0x109},
> + {0x90056, 0x40},
> + {0x90057, 0x630},
> + {0x90058, 0x179},
> + {0x90059, 0x1},
> + {0x9005a, 0x618},
> + {0x9005b, 0x109},
> + {0x9005c, 0x40c0},
> + {0x9005d, 0x630},
> + {0x9005e, 0x149},
> + {0x9005f, 0x8},
> + {0x90060, 0x4},
> + {0x90061, 0x48},
> + {0x90062, 0x4040},
> + {0x90063, 0x630},
> + {0x90064, 0x149},
> + {0x90065, 0x0},
> + {0x90066, 0x4},
> + {0x90067, 0x48},
> + {0x90068, 0x40},
> + {0x90069, 0x630},
> + {0x9006a, 0x149},
> + {0x9006b, 0x10},
> + {0x9006c, 0x4},
> + {0x9006d, 0x18},
> + {0x9006e, 0x0},
> + {0x9006f, 0x4},
> + {0x90070, 0x78},
> + {0x90071, 0x549},
> + {0x90072, 0x630},
> + {0x90073, 0x159},
> + {0x90074, 0xd49},
> + {0x90075, 0x630},
> + {0x90076, 0x159},
> + {0x90077, 0x94a},
> + {0x90078, 0x630},
> + {0x90079, 0x159},
> + {0x9007a, 0x441},
> + {0x9007b, 0x630},
> + {0x9007c, 0x149},
> + {0x9007d, 0x42},
> + {0x9007e, 0x630},
> + {0x9007f, 0x149},
> + {0x90080, 0x1},
> + {0x90081, 0x630},
> + {0x90082, 0x149},
> + {0x90083, 0x0},
> + {0x90084, 0xe0},
> + {0x90085, 0x109},
> + {0x90086, 0xa},
> + {0x90087, 0x10},
> + {0x90088, 0x109},
> + {0x90089, 0x9},
> + {0x9008a, 0x3c0},
> + {0x9008b, 0x149},
> + {0x9008c, 0x9},
> + {0x9008d, 0x3c0},
> + {0x9008e, 0x159},
> + {0x9008f, 0x18},
> + {0x90090, 0x10},
> + {0x90091, 0x109},
> + {0x90092, 0x0},
> + {0x90093, 0x3c0},
> + {0x90094, 0x109},
> + {0x90095, 0x18},
> + {0x90096, 0x4},
> + {0x90097, 0x48},
> + {0x90098, 0x18},
> + {0x90099, 0x4},
> + {0x9009a, 0x58},
> + {0x9009b, 0xa},
> + {0x9009c, 0x10},
> + {0x9009d, 0x109},
> + {0x9009e, 0x2},
> + {0x9009f, 0x10},
> + {0x900a0, 0x109},
> + {0x900a1, 0x5},
> + {0x900a2, 0x7c0},
> + {0x900a3, 0x109},
> + {0x900a4, 0x10},
> + {0x900a5, 0x10},
> + {0x900a6, 0x109},
> + {0x40000, 0x811},
> + {0x40020, 0x880},
> + {0x40040, 0x0},
> + {0x40060, 0x0},
> + {0x40001, 0x4008},
> + {0x40021, 0x83},
> + {0x40041, 0x4f},
> + {0x40061, 0x0},
> + {0x40002, 0x4040},
> + {0x40022, 0x83},
> + {0x40042, 0x51},
> + {0x40062, 0x0},
> + {0x40003, 0x811},
> + {0x40023, 0x880},
> + {0x40043, 0x0},
> + {0x40063, 0x0},
> + {0x40004, 0x720},
> + {0x40024, 0xf},
> + {0x40044, 0x1740},
> + {0x40064, 0x0},
> + {0x40005, 0x16},
> + {0x40025, 0x83},
> + {0x40045, 0x4b},
> + {0x40065, 0x0},
> + {0x40006, 0x716},
> + {0x40026, 0xf},
> + {0x40046, 0x2001},
> + {0x40066, 0x0},
> + {0x40007, 0x716},
> + {0x40027, 0xf},
> + {0x40047, 0x2800},
> + {0x40067, 0x0},
> + {0x40008, 0x716},
> + {0x40028, 0xf},
> + {0x40048, 0xf00},
> + {0x40068, 0x0},
> + {0x40009, 0x720},
> + {0x40029, 0xf},
> + {0x40049, 0x1400},
> + {0x40069, 0x0},
> + {0x4000a, 0xe08},
> + {0x4002a, 0xc15},
> + {0x4004a, 0x0},
> + {0x4006a, 0x0},
> + {0x4000b, 0x623},
> + {0x4002b, 0x15},
> + {0x4004b, 0x0},
> + {0x4006b, 0x0},
> + {0x4000c, 0x4028},
> + {0x4002c, 0x80},
> + {0x4004c, 0x0},
> + {0x4006c, 0x0},
> + {0x4000d, 0xe08},
> + {0x4002d, 0xc1a},
> + {0x4004d, 0x0},
> + {0x4006d, 0x0},
> + {0x4000e, 0x623},
> + {0x4002e, 0x1a},
> + {0x4004e, 0x0},
> + {0x4006e, 0x0},
> + {0x4000f, 0x4040},
> + {0x4002f, 0x80},
> + {0x4004f, 0x0},
> + {0x4006f, 0x0},
> + {0x40010, 0x2604},
> + {0x40030, 0x15},
> + {0x40050, 0x0},
> + {0x40070, 0x0},
> + {0x40011, 0x708},
> + {0x40031, 0x5},
> + {0x40051, 0x0},
> + {0x40071, 0x2002},
> + {0x40012, 0x8},
> + {0x40032, 0x80},
> + {0x40052, 0x0},
> + {0x40072, 0x0},
> + {0x40013, 0x2604},
> + {0x40033, 0x1a},
> + {0x40053, 0x0},
> + {0x40073, 0x0},
> + {0x40014, 0x708},
> + {0x40034, 0xa},
> + {0x40054, 0x0},
> + {0x40074, 0x2002},
> + {0x40015, 0x4040},
> + {0x40035, 0x80},
> + {0x40055, 0x0},
> + {0x40075, 0x0},
> + {0x40016, 0x60a},
> + {0x40036, 0x15},
> + {0x40056, 0x1200},
> + {0x40076, 0x0},
> + {0x40017, 0x61a},
> + {0x40037, 0x15},
> + {0x40057, 0x1300},
> + {0x40077, 0x0},
> + {0x40018, 0x60a},
> + {0x40038, 0x1a},
> + {0x40058, 0x1200},
> + {0x40078, 0x0},
> + {0x40019, 0x642},
> + {0x40039, 0x1a},
> + {0x40059, 0x1300},
> + {0x40079, 0x0},
> + {0x4001a, 0x4808},
> + {0x4003a, 0x880},
> + {0x4005a, 0x0},
> + {0x4007a, 0x0},
> + {0x900a7, 0x0},
> + {0x900a8, 0x790},
> + {0x900a9, 0x11a},
> + {0x900aa, 0x8},
> + {0x900ab, 0x7aa},
> + {0x900ac, 0x2a},
> + {0x900ad, 0x10},
> + {0x900ae, 0x7b2},
> + {0x900af, 0x2a},
> + {0x900b0, 0x0},
> + {0x900b1, 0x7c8},
> + {0x900b2, 0x109},
> + {0x900b3, 0x10},
> + {0x900b4, 0x2a8},
> + {0x900b5, 0x129},
> + {0x900b6, 0x8},
> + {0x900b7, 0x370},
> + {0x900b8, 0x129},
> + {0x900b9, 0xa},
> + {0x900ba, 0x3c8},
> + {0x900bb, 0x1a9},
> + {0x900bc, 0xc},
> + {0x900bd, 0x408},
> + {0x900be, 0x199},
> + {0x900bf, 0x14},
> + {0x900c0, 0x790},
> + {0x900c1, 0x11a},
> + {0x900c2, 0x8},
> + {0x900c3, 0x4},
> + {0x900c4, 0x18},
> + {0x900c5, 0xe},
> + {0x900c6, 0x408},
> + {0x900c7, 0x199},
> + {0x900c8, 0x8},
> + {0x900c9, 0x8568},
> + {0x900ca, 0x108},
> + {0x900cb, 0x18},
> + {0x900cc, 0x790},
> + {0x900cd, 0x16a},
> + {0x900ce, 0x8},
> + {0x900cf, 0x1d8},
> + {0x900d0, 0x169},
> + {0x900d1, 0x10},
> + {0x900d2, 0x8558},
> + {0x900d3, 0x168},
> + {0x900d4, 0x70},
> + {0x900d5, 0x788},
> + {0x900d6, 0x16a},
> + {0x900d7, 0x1ff8},
> + {0x900d8, 0x85a8},
> + {0x900d9, 0x1e8},
> + {0x900da, 0x50},
> + {0x900db, 0x798},
> + {0x900dc, 0x16a},
> + {0x900dd, 0x60},
> + {0x900de, 0x7a0},
> + {0x900df, 0x16a},
> + {0x900e0, 0x8},
> + {0x900e1, 0x8310},
> + {0x900e2, 0x168},
> + {0x900e3, 0x8},
> + {0x900e4, 0xa310},
> + {0x900e5, 0x168},
> + {0x900e6, 0xa},
> + {0x900e7, 0x408},
> + {0x900e8, 0x169},
> + {0x900e9, 0x6e},
> + {0x900ea, 0x0},
> + {0x900eb, 0x68},
> + {0x900ec, 0x0},
> + {0x900ed, 0x408},
> + {0x900ee, 0x169},
> + {0x900ef, 0x0},
> + {0x900f0, 0x8310},
> + {0x900f1, 0x168},
> + {0x900f2, 0x0},
> + {0x900f3, 0xa310},
> + {0x900f4, 0x168},
> + {0x900f5, 0x1ff8},
> + {0x900f6, 0x85a8},
> + {0x900f7, 0x1e8},
> + {0x900f8, 0x68},
> + {0x900f9, 0x798},
> + {0x900fa, 0x16a},
> + {0x900fb, 0x78},
> + {0x900fc, 0x7a0},
> + {0x900fd, 0x16a},
> + {0x900fe, 0x68},
> + {0x900ff, 0x790},
> + {0x90100, 0x16a},
> + {0x90101, 0x8},
> + {0x90102, 0x8b10},
> + {0x90103, 0x168},
> + {0x90104, 0x8},
> + {0x90105, 0xab10},
> + {0x90106, 0x168},
> + {0x90107, 0xa},
> + {0x90108, 0x408},
> + {0x90109, 0x169},
> + {0x9010a, 0x58},
> + {0x9010b, 0x0},
> + {0x9010c, 0x68},
> + {0x9010d, 0x0},
> + {0x9010e, 0x408},
> + {0x9010f, 0x169},
> + {0x90110, 0x0},
> + {0x90111, 0x8b10},
> + {0x90112, 0x168},
> + {0x90113, 0x0},
> + {0x90114, 0xab10},
> + {0x90115, 0x168},
> + {0x90116, 0x0},
> + {0x90117, 0x1d8},
> + {0x90118, 0x169},
> + {0x90119, 0x80},
> + {0x9011a, 0x790},
> + {0x9011b, 0x16a},
> + {0x9011c, 0x18},
> + {0x9011d, 0x7aa},
> + {0x9011e, 0x6a},
> + {0x9011f, 0xa},
> + {0x90120, 0x0},
> + {0x90121, 0x1e9},
> + {0x90122, 0x8},
> + {0x90123, 0x8080},
> + {0x90124, 0x108},
> + {0x90125, 0xf},
> + {0x90126, 0x408},
> + {0x90127, 0x169},
> + {0x90128, 0xc},
> + {0x90129, 0x0},
> + {0x9012a, 0x68},
> + {0x9012b, 0x9},
> + {0x9012c, 0x0},
> + {0x9012d, 0x1a9},
> + {0x9012e, 0x0},
> + {0x9012f, 0x408},
> + {0x90130, 0x169},
> + {0x90131, 0x0},
> + {0x90132, 0x8080},
> + {0x90133, 0x108},
> + {0x90134, 0x8},
> + {0x90135, 0x7aa},
> + {0x90136, 0x6a},
> + {0x90137, 0x0},
> + {0x90138, 0x8568},
> + {0x90139, 0x108},
> + {0x9013a, 0xb7},
> + {0x9013b, 0x790},
> + {0x9013c, 0x16a},
> + {0x9013d, 0x1f},
> + {0x9013e, 0x0},
> + {0x9013f, 0x68},
> + {0x90140, 0x8},
> + {0x90141, 0x8558},
> + {0x90142, 0x168},
> + {0x90143, 0xf},
> + {0x90144, 0x408},
> + {0x90145, 0x169},
> + {0x90146, 0xc},
> + {0x90147, 0x0},
> + {0x90148, 0x68},
> + {0x90149, 0x0},
> + {0x9014a, 0x408},
> + {0x9014b, 0x169},
> + {0x9014c, 0x0},
> + {0x9014d, 0x8558},
> + {0x9014e, 0x168},
> + {0x9014f, 0x8},
> + {0x90150, 0x3c8},
> + {0x90151, 0x1a9},
> + {0x90152, 0x3},
> + {0x90153, 0x370},
> + {0x90154, 0x129},
> + {0x90155, 0x20},
> + {0x90156, 0x2aa},
> + {0x90157, 0x9},
> + {0x90158, 0x0},
> + {0x90159, 0x400},
> + {0x9015a, 0x10e},
> + {0x9015b, 0x8},
> + {0x9015c, 0xe8},
> + {0x9015d, 0x109},
> + {0x9015e, 0x0},
> + {0x9015f, 0x8140},
> + {0x90160, 0x10c},
> + {0x90161, 0x10},
> + {0x90162, 0x8138},
> + {0x90163, 0x10c},
> + {0x90164, 0x8},
> + {0x90165, 0x7c8},
> + {0x90166, 0x101},
> + {0x90167, 0x8},
> + {0x90168, 0x0},
> + {0x90169, 0x8},
> + {0x9016a, 0x8},
> + {0x9016b, 0x448},
> + {0x9016c, 0x109},
> + {0x9016d, 0xf},
> + {0x9016e, 0x7c0},
> + {0x9016f, 0x109},
> + {0x90170, 0x0},
> + {0x90171, 0xe8},
> + {0x90172, 0x109},
> + {0x90173, 0x47},
> + {0x90174, 0x630},
> + {0x90175, 0x109},
> + {0x90176, 0x8},
> + {0x90177, 0x618},
> + {0x90178, 0x109},
> + {0x90179, 0x8},
> + {0x9017a, 0xe0},
> + {0x9017b, 0x109},
> + {0x9017c, 0x0},
> + {0x9017d, 0x7c8},
> + {0x9017e, 0x109},
> + {0x9017f, 0x8},
> + {0x90180, 0x8140},
> + {0x90181, 0x10c},
> + {0x90182, 0x0},
> + {0x90183, 0x1},
> + {0x90184, 0x8},
> + {0x90185, 0x8},
> + {0x90186, 0x4},
> + {0x90187, 0x8},
> + {0x90188, 0x8},
> + {0x90189, 0x7c8},
> + {0x9018a, 0x101},
> + {0x90006, 0x0},
> + {0x90007, 0x0},
> + {0x90008, 0x8},
> + {0x90009, 0x0},
> + {0x9000a, 0x0},
> + {0x9000b, 0x0},
> + {0xd00e7, 0x400},
> + {0x90017, 0x0},
> + {0x9001f, 0x2a},
> + {0x90026, 0x6a},
> + {0x400d0, 0x0},
> + {0x400d1, 0x101},
> + {0x400d2, 0x105},
> + {0x400d3, 0x107},
> + {0x400d4, 0x10f},
> + {0x400d5, 0x202},
> + {0x400d6, 0x20a},
> + {0x400d7, 0x20b},
> + {0x2003a, 0x2},
> + {0x2000b, 0x5d},
> + {0x2000c, 0xbb},
> + {0x2000d, 0x753},
> + {0x2000e, 0x2c},
> + {0x12000b, 0xc},
> + {0x12000c, 0x19},
> + {0x12000d, 0xfa},
> + {0x12000e, 0x10},
> + {0x22000b, 0x3},
> + {0x22000c, 0x6},
> + {0x22000d, 0x3e},
> + {0x22000e, 0x10},
> + {0x9000c, 0x0},
> + {0x9000d, 0x173},
> + {0x9000e, 0x60},
> + {0x9000f, 0x6110},
> + {0x90010, 0x2152},
> + {0x90011, 0xdfbd},
> + {0x90012, 0x60},
> + {0x90013, 0x6152},
> + {0x20010, 0x5a},
> + {0x20011, 0x3},
> + {0x120010, 0x5a},
> + {0x120011, 0x3},
> + {0x220010, 0x5a},
> + {0x220011, 0x3},
> + {0x40080, 0xe0},
> + {0x40081, 0x12},
> + {0x40082, 0xe0},
> + {0x40083, 0x12},
> + {0x40084, 0xe0},
> + {0x40085, 0x12},
> + {0x140080, 0xe0},
> + {0x140081, 0x12},
> + {0x140082, 0xe0},
> + {0x140083, 0x12},
> + {0x140084, 0xe0},
> + {0x140085, 0x12},
> + {0x240080, 0xe0},
> + {0x240081, 0x12},
> + {0x240082, 0xe0},
> + {0x240083, 0x12},
> + {0x240084, 0xe0},
> + {0x240085, 0x12},
> + {0x400fd, 0xf},
> + {0x10011, 0x1},
> + {0x10012, 0x1},
> + {0x10013, 0x180},
> + {0x10018, 0x1},
> + {0x10002, 0x6209},
> + {0x100b2, 0x1},
> + {0x101b4, 0x1},
> + {0x102b4, 0x1},
> + {0x103b4, 0x1},
> + {0x104b4, 0x1},
> + {0x105b4, 0x1},
> + {0x106b4, 0x1},
> + {0x107b4, 0x1},
> + {0x108b4, 0x1},
> + {0x11011, 0x1},
> + {0x11012, 0x1},
> + {0x11013, 0x180},
> + {0x11018, 0x1},
> + {0x11002, 0x6209},
> + {0x110b2, 0x1},
> + {0x111b4, 0x1},
> + {0x112b4, 0x1},
> + {0x113b4, 0x1},
> + {0x114b4, 0x1},
> + {0x115b4, 0x1},
> + {0x116b4, 0x1},
> + {0x117b4, 0x1},
> + {0x118b4, 0x1},
> + {0x12011, 0x1},
> + {0x12012, 0x1},
> + {0x12013, 0x180},
> + {0x12018, 0x1},
> + {0x12002, 0x6209},
> + {0x120b2, 0x1},
> + {0x121b4, 0x1},
> + {0x122b4, 0x1},
> + {0x123b4, 0x1},
> + {0x124b4, 0x1},
> + {0x125b4, 0x1},
> + {0x126b4, 0x1},
> + {0x127b4, 0x1},
> + {0x128b4, 0x1},
> + {0x13011, 0x1},
> + {0x13012, 0x1},
> + {0x13013, 0x180},
> + {0x13018, 0x1},
> + {0x13002, 0x6209},
> + {0x130b2, 0x1},
> + {0x131b4, 0x1},
> + {0x132b4, 0x1},
> + {0x133b4, 0x1},
> + {0x134b4, 0x1},
> + {0x135b4, 0x1},
> + {0x136b4, 0x1},
> + {0x137b4, 0x1},
> + {0x138b4, 0x1},
> + {0x2003a, 0x2},
> + {0xc0080, 0x2},
> + {0xd0000, 0x1}
> +};
> +
> +struct dram_fsp_msg ddr_dram_fsp_msg[] = {
> + {
> + /* P0 3000mts 1D */
> + .drate = 3000,
> + .fw_type = FW_1D_IMAGE,
> + .fsp_cfg = ddr_fsp0_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
> + },
> + {
> + /* P1 400mts 1D */
> + .drate = 400,
> + .fw_type = FW_1D_IMAGE,
> + .fsp_cfg = ddr_fsp1_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
> + },
> + {
> + /* P2 100mts 1D */
> + .drate = 100,
> + .fw_type = FW_1D_IMAGE,
> + .fsp_cfg = ddr_fsp2_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
> + },
> + {
> + /* P0 3000mts 2D */
> + .drate = 3000,
> + .fw_type = FW_2D_IMAGE,
> + .fsp_cfg = ddr_fsp0_2d_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
> + },
> +};
> +
> +/* ddr timing config params */
> +struct dram_timing_info dram_timing = {
> + .ddrc_cfg = ddr_ddrc_cfg,
> + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
> + .ddrphy_cfg = ddr_ddrphy_cfg,
> + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
> + .fsp_msg = ddr_dram_fsp_msg,
> + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
> + .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
> + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
> + .ddrphy_pie = ddr_phy_pie,
> + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
> + .fsp_table = { 3000, 400, 100, },
> +};
> +
> diff --git a/board/toradex/verdin-imx8mm/spl.c
> b/board/toradex/verdin-imx8mm/spl.c
> new file mode 100644
> index 0000000000..2ca9442983
> --- /dev/null
> +++ b/board/toradex/verdin-imx8mm/spl.c
> @@ -0,0 +1,183 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 Toradex AG
> + */
> +
> +#include <common.h>
> +#include <cpu_func.h>
> +#include <hang.h>
> +#include <spl.h>
> +
> +#include <asm/io.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx8mm_pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/mach-imx/boot_mode.h>
> +#include <asm/arch/ddr.h>
> +
> +#include <dm/uclass.h>
> +#include <dm/device.h>
> +#include <dm/uclass-internal.h>
> +#include <dm/device-internal.h>
> +
> +#include <power/pmic.h>
> +#include <power/bd71837.h>
> +
I prefer header files to be alphabetically ordered.
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int spl_board_boot_device(enum boot_device boot_dev_spl)
> +{
> + switch (boot_dev_spl) {
> + case MMC1_BOOT:
> + return BOOT_DEVICE_MMC1;
> + case SD2_BOOT:
> + case MMC2_BOOT:
> + return BOOT_DEVICE_MMC2;
> + case SD3_BOOT:
> + case MMC3_BOOT:
> + return BOOT_DEVICE_MMC1;
> + case USB_BOOT:
> + return BOOT_DEVICE_BOARD;
> + default:
> + return BOOT_DEVICE_NONE;
> + }
> +}
> +
> +void spl_dram_init(void)
> +{
> + ddr_init(&dram_timing);
> +}
> +
> +void spl_board_init(void)
> +{
> + /* Serial download mode */
> + if (is_usb_boot()) {
> + puts("Back to ROM, SDP\n");
> + restore_boot_params();
> + }
> + puts("Normal Boot\n");
> +}
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> + /* Just empty function now - can't decide what to choose */
> + debug("%s: %s\n", __func__, name);
> +
> + return 0;
> +}
> +#endif
> +
> +#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE |
> PAD_CTL_DSE4)
> +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE |
> PAD_CTL_PUE | PAD_CTL_PE)
> +
> +/* Verdin UART_3, Console/Debug UART */
> +static iomux_v3_cfg_t const uart_pads[] = {
> + IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> + IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const wdog_pads[] = {
> + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B |
> MUX_PAD_CTRL(WDOG_PAD_CTRL),
> +};
> +
> +int board_early_init_f(void)
> +{
> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> +
> + imx_iomux_v3_setup_multiple_pads(wdog_pads,
> ARRAY_SIZE(wdog_pads));
> +
> + set_wdog_reset(wdog);
> +
> + imx_iomux_v3_setup_multiple_pads(uart_pads,
> ARRAY_SIZE(uart_pads));
> +
> + return 0;
> +}
> +
> +int power_init_board(void)
> +{
> + struct udevice *dev;
> + int ret;
> +
> + ret = pmic_get("pmic at 4b", &dev);
> + if (ret == -ENODEV) {
> + puts("No pmic\n");
> + return 0;
> + }
> + if (ret != 0)
> + return ret;
> +
> + /* decrease RESET key long push time from the default 10s to
> 10ms */
> + pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
> +
> + /* unlock the PMIC regs */
> + pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
> +
> + /* increase VDD_SOC to typical value 0.85v before first DRAM
> access */
> + pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
> +
> + /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
> + pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
> +
> +#ifndef CONFIG_IMX8M_LPDDR4
> + /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
> + pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
> +#endif
> +
> + /* lock the PMIC regs */
> + pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
> +
> + return 0;
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> + struct udevice *dev;
> + int ret;
> +
> + arch_cpu_init();
> +
> + init_uart_clk(0);
> +
> + board_early_init_f();
> +
> + timer_init();
> +
> + preloader_console_init();
> +
> + /* Clear the BSS. */
> + memset(__bss_start, 0, __bss_end - __bss_start);
> +
> + ret = spl_early_init();
> + if (ret) {
> + debug("spl_early_init() failed: %d\n", ret);
> + hang();
> + }
> +
> + ret = uclass_get_device_by_name(UCLASS_CLK,
> + "clock-controller at 30380000",
> + &dev);
> + if (ret < 0) {
> + printf("Failed to find clock node. Check device
> tree\n");
> + hang();
> + }
> +
> + enable_tzc380();
> +
> + power_init_board();
> +
> + /* DDR initialization */
> + spl_dram_init();
> +
> + board_init_r(NULL, 0);
> +}
> +
> +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const
> argv[])
> +{
> + puts("resetting ...\n");
> +
> + reset_cpu(WDOG1_BASE_ADDR);
> +
> + return 0;
> +}
> diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
> b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
> new file mode 100644
> index 0000000000..718849e9f6
> --- /dev/null
> +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 Toradex AG
> + */
> +
> +#include <common.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +
> +#include <asm/arch/clock.h>
> +#include <asm/io.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> + gd->ram_size = PHYS_SDRAM_SIZE;
Wondering whether or not this could be taken from the DDR controller's
configured size as on i.MX 6/7.
> +
> + return 0;
> +}
> +
> +#if IS_ENABLED(CONFIG_FEC_MXC)
> +static int setup_fec(void)
> +{
> + struct iomuxc_gpr_base_regs *gpr =
> + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
> +
> + /* Use 125M anatop REF_CLK1 for ENET1, not from external */
> + clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
> +
> + return 0;
> +}
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> + /* enable rgmii rxc skew and phy mode select to RGMII copper */
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> +
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> +
> + if (phydev->drv->config)
> + phydev->drv->config(phydev);
> + return 0;
> +}
> +#endif
> +
> +int board_init(void)
> +{
> + if (IS_ENABLED(CONFIG_FEC_MXC))
> + setup_fec();
> +
> + return 0;
> +}
> +
> +int board_mmc_get_env_dev(int devno)
> +{
> + return devno;
> +}
> +
> +int board_late_init(void)
> +{
> + return 0;
> +}
> +
> +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
> +int ft_board_setup(void *blob, bd_t *bd)
> +{
> + return 0;
> +}
> +#endif
> diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-
> imx8mm_defconfig
> new file mode 100644
> index 0000000000..87fbed8456
> --- /dev/null
> +++ b/configs/verdin-imx8mm_defconfig
> @@ -0,0 +1,88 @@
> +CONFIG_ARM=y
> +CONFIG_SPL_SYS_ICACHE_OFF=y
> +CONFIG_SPL_SYS_DCACHE_OFF=y
> +CONFIG_ARCH_IMX8M=y
> +CONFIG_SYS_TEXT_BASE=0x40200000
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x10000
> +CONFIG_SYS_I2C_MXC_I2C1=y
> +CONFIG_SYS_I2C_MXC_I2C2=y
> +CONFIG_SYS_I2C_MXC_I2C3=y
> +CONFIG_ENV_SIZE=0x2000
> +CONFIG_ENV_OFFSET=0xFFFFDE00
> +CONFIG_DM_GPIO=y
> +CONFIG_TARGET_VERDIN_IMX8MM=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> +CONFIG_SPL=y
> +CONFIG_SPL_TEXT_BASE=0x7E1000
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_FIT=y
> +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> +CONFIG_OF_SYSTEM_SETUP=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/verdin-
> imx8mm/imximage.cfg"
> +# CONFIG_USE_BOOTCOMMAND is not set
> +CONFIG_BOARD_LATE_INIT=y
> +# CONFIG_DISPLAY_BOARDINFO is not set
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_SPL_BOARD_INIT=y
> +CONFIG_SPL_SEPARATE_BSS=y
> +CONFIG_SPL_I2C_SUPPORT=y
> +CONFIG_SPL_POWER_SUPPORT=y
> +CONFIG_SPL_USB_HOST_SUPPORT=y
> +CONFIG_SYS_PROMPT="Verdin iMX8MM # "
> +# CONFIG_CMD_EXPORTENV is not set
> +# CONFIG_CMD_IMPORTENV is not set
> +# CONFIG_CMD_CRC32 is not set
> +CONFIG_CMD_CLK=y
> +CONFIG_CMD_FUSE=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_CMD_EXT4_WRITE=y
> +# CONFIG_ISO_PARTITION is not set
> +# CONFIG_EFI_PARTITION is not set
> +CONFIG_OF_CONTROL=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-verdin"
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> +CONFIG_SPL_DM=y
> +CONFIG_SPL_CLK_COMPOSITE_CCF=y
> +CONFIG_CLK_COMPOSITE_CCF=y
> +CONFIG_SPL_CLK_IMX8MM=y
> +CONFIG_CLK_IMX8MM=y
> +CONFIG_MXC_GPIO=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_MXC=y
> +CONFIG_DM_MMC=y
> +CONFIG_SUPPORT_EMMC_BOOT=y
> +CONFIG_FSL_ESDHC_IMX=y
> +CONFIG_PHYLIB=y
> +CONFIG_PHY_ATHEROS=y
> +CONFIG_PHY_MICREL=y
> +CONFIG_PHY_MICREL_KSZ90X1=y
> +CONFIG_DM_ETH=y
> +CONFIG_FEC_MXC=y
> +CONFIG_MII=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_PINCTRL_IMX8M=y
> +CONFIG_DM_PMIC=y
> +CONFIG_SPL_DM_PMIC_BD71837=y
> +CONFIG_DM_PMIC_PFUZE100=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_MXC_UART=y
> +CONFIG_SYSRESET=y
> +CONFIG_SYSRESET_PSCI=y
> +CONFIG_DM_THERMAL=y
> diff --git a/include/configs/verdin-imx8mm.h
> b/include/configs/verdin-imx8mm.h
> new file mode 100644
> index 0000000000..1caa03e8b9
> --- /dev/null
> +++ b/include/configs/verdin-imx8mm.h
> @@ -0,0 +1,121 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2019 Toradex AG
> + */
> +
> +#ifndef __VERDIN_IMX8MM_H
> +#define __VERDIN_IMX8MM_H
> +
> +#include <linux/sizes.h>
> +#include <asm/arch/imx-regs.h>
> +
> +#ifdef CONFIG_SECURE_BOOT
> +#define CONFIG_CSF_SIZE SZ_8K
> +#endif
> +
> +#define CONFIG_SPL_MAX_SIZE (148 * 1024)
> +#define CONFIG_SYS_MONITOR_LEN SZ_512K
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> +#define CONFIG_SYS_UBOOT_BASE \
> + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
> 512)
> +
> +#ifdef CONFIG_SPL_BUILD
> +#define CONFIG_SPL_STACK 0x920000
> +#define CONFIG_SPL_BSS_START_ADDR 0x910000
> +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
> +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
> +
> +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
> +#define CONFIG_MALLOC_F_ADDR 0x930000
> +/* For RAW image gives a error info not panic */
> +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
> +
> +#endif
> +
> +#define MEM_LAYOUT_ENV_SETTINGS \
> + "fdt_addr_r=0x44000000\0" \
> + "kernel_addr_r=0x42000000\0" \
> + "ramdisk_addr_r=0x46400000\0" \
> + "scriptaddr=0x46000000\0"
> +
> +#define CONFIG_LOADADDR 0x40480000
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +/* Enable Distro Boot */
> +#ifndef CONFIG_SPL_BUILD
> +#define BOOT_TARGET_DEVICES(func) \
> + func(MMC, mmc, 1) \
> + func(MMC, mmc, 0) \
> + func(DHCP, dhcp, na)
> +#include <config_distro_bootcmd.h>
> +#undef CONFIG_ISO_PARTITION
> +#else
> +#define BOOTENV
> +#endif
> +
> +/* Initial environment variables */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + BOOTENV \
> + MEM_LAYOUT_ENV_SETTINGS \
> + "bootcmd_mfg=fastboot 0\0" \
> + "console=ttymxc0\0" \
> + "fdt_addr=0x43000000\0" \
> + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
> + "initrd_addr=0x43800000\0" \
> + "initrd_high=0xffffffffffffffff\0" \
> + "kernel_image=Image\0" \
> + "setup=setenv setupargs console=${console},${baudrate} " \
> + "console=tty1 consoleblank=0 earlycon\0"
Quite minimalistic. At least the update_uboot wrapper similar to the
one found in Apalis iMX8 resp. Colibri iMX8X could be added.
> +
> +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
> +#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
> +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /*
> USDHC2 */
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN SZ_32M
> +#define CONFIG_SYS_SDRAM_BASE 0x40000000
> +
> +/* SDRAM configuration */
> +#define PHYS_SDRAM 0x40000000
> +#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
> +
> +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_STA
> RT + \
> + (PHYS_SDRAM_SIZE >> 1))
> +
> +/* UART */
> +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
> +
> +/* Monitor Command Prompt */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#define CONFIG_SYS_CBSIZE 2048
> +#define CONFIG_SYS_MAXARGS 64
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> + sizeof(CONFIG_SYS_PROMPT) + 16)
> +/* USDHC */
> +#define CONFIG_FSL_USDHC
> +#define CONFIG_SYS_FSL_USDHC_NUM 2
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
> +#define CONFIG_SYS_I2C_SPEED 100000
> +
> +/* ENET */
> +#define CONFIG_ETHPRIME "FEC"
> +#define CONFIG_FEC_XCV_TYPE RGMII
> +#define CONFIG_FEC_MXC_PHYADDR 7
> +#define FEC_QUIRK_ENET_MAC
> +#define IMX_FEC_BASE 0x30BE0000
> +
> +#endif /*_VERDIN_IMX8MM_H */
> +
Test looks good. Thanks!
Cheers
Marcel
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