[PATCH 070/108] x86: coral: Add ACPI tables for coral
Simon Glass
sjg at chromium.org
Mon Jan 27 06:06:17 CET 2020
This device has a large set of ACPI tables. Bring these in from coreboot
so that full functionality is available (apart from SMI).
Signed-off-by: Simon Glass <sjg at chromium.org>
---
board/google/chromebook_coral/Makefile | 1 +
.../chromebook_coral/baseboard_dptf.asl | 71 ++++++++++++
board/google/chromebook_coral/coral.c | 104 ++++++++++++++++++
board/google/chromebook_coral/dsdt.asl | 60 ++++++++++
.../google/chromebook_coral/variant_dptf.asl | 6 +
board/google/chromebook_coral/variant_ec.h | 75 +++++++++++++
board/google/chromebook_coral/variant_gpio.h | 63 +++++++++++
7 files changed, 380 insertions(+)
create mode 100644 board/google/chromebook_coral/baseboard_dptf.asl
create mode 100644 board/google/chromebook_coral/dsdt.asl
create mode 100644 board/google/chromebook_coral/variant_dptf.asl
create mode 100644 board/google/chromebook_coral/variant_ec.h
create mode 100644 board/google/chromebook_coral/variant_gpio.h
diff --git a/board/google/chromebook_coral/Makefile b/board/google/chromebook_coral/Makefile
index 6a27ce3da1..f7a0ca6cc0 100644
--- a/board/google/chromebook_coral/Makefile
+++ b/board/google/chromebook_coral/Makefile
@@ -3,3 +3,4 @@
# Copyright 2019 Google LLC
obj-y += coral.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/google/chromebook_coral/baseboard_dptf.asl b/board/google/chromebook_coral/baseboard_dptf.asl
new file mode 100644
index 0000000000..5da963a670
--- /dev/null
+++ b/board/google/chromebook_coral/baseboard_dptf.asl
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ */
+
+#define DPTF_CPU_PASSIVE 95
+#define DPTF_CPU_CRITICAL 105
+
+#define DPTF_TSR0_SENSOR_ID 0
+#define DPTF_TSR0_SENSOR_NAME "Battery"
+#define DPTF_TSR0_PASSIVE 120
+#define DPTF_TSR0_CRITICAL 125
+
+#define DPTF_TSR1_SENSOR_ID 1
+#define DPTF_TSR1_SENSOR_NAME "Ambient"
+#define DPTF_TSR1_PASSIVE 46
+#define DPTF_TSR1_CRITICAL 75
+
+#define DPTF_TSR2_SENSOR_ID 2
+#define DPTF_TSR2_SENSOR_NAME "Charger"
+#define DPTF_TSR2_PASSIVE 58
+#define DPTF_TSR2_CRITICAL 90
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 2 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 3000, /* PowerLimitMinimum */
+ 12000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 8000, /* PowerLimitMinimum */
+ 15000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c
index 4e34710b97..58b8e7293b 100644
--- a/board/google/chromebook_coral/coral.c
+++ b/board/google/chromebook_coral/coral.c
@@ -4,6 +4,19 @@
*/
#include <common.h>
+#include <acpigen.h>
+#include <dm.h>
+#include <asm-generic/gpio.h>
+#include <asm/intel_pinctrl.h>
+#include <dm/acpi.h>
+#include "variant_gpio.h"
+
+struct cros_gpio_info {
+ const char *linux_name;
+ enum cros_gpio_t type;
+ int gpio_num;
+ int flags;
+};
int arch_misc_init(void)
{
@@ -17,3 +30,94 @@ int board_run_command(const char *cmdline)
return 0;
}
+
+int chromeos_get_gpio(const struct udevice *dev, const char *prop,
+ enum cros_gpio_t type, struct cros_gpio_info *info)
+{
+ struct udevice *pinctrl;
+ struct gpio_desc desc;
+ int ret;
+
+ ret = gpio_request_by_name((struct udevice *)dev, prop, 0, &desc, 0);
+ if (ret == -ENOTBLK)
+ info->gpio_num = CROS_GPIO_VIRTUAL;
+ else if (ret)
+ return log_msg_ret("gpio", ret);
+ else
+ info->gpio_num = desc.offset;
+ info->linux_name = dev_read_string(desc.dev, "linux-name");
+ if (!info->linux_name)
+ return log_msg_ret("linux-name", -ENOENT);
+ info->type = type;
+ /* Get ACPI pin from GPIO library if available */
+ if (info->gpio_num != CROS_GPIO_VIRTUAL) {
+ pinctrl = dev_get_parent(desc.dev);
+ info->gpio_num = intel_pinctrl_get_acpi_pin(pinctrl,
+ info->gpio_num);
+ }
+ info->flags = desc.flags & GPIOD_ACTIVE_LOW ? CROS_GPIO_ACTIVE_LOW :
+ CROS_GPIO_ACTIVE_HIGH;
+
+ return 0;
+}
+
+static int chromeos_acpi_gpio_generate(const struct udevice *dev,
+ struct acpi_ctx *ctx)
+{
+ struct cros_gpio_info info[3];
+ int count, i;
+ int ret;
+
+ count = 3;
+ ret = chromeos_get_gpio(dev, "recovery-gpios", CROS_GPIO_REC, &info[0]);
+ if (ret)
+ return log_msg_ret("rec", ret);
+ ret = chromeos_get_gpio(dev, "write-protect-gpios", CROS_GPIO_WP,
+ &info[1]);
+ if (ret)
+ return log_msg_ret("rec", ret);
+ ret = chromeos_get_gpio(dev, "phase-enforce-gpios", CROS_GPIO_PE,
+ &info[2]);
+ if (ret)
+ return log_msg_ret("rec", ret);
+ acpigen_write_scope(ctx, "\\");
+ acpigen_write_name(ctx, "OIPG");
+ acpigen_write_package(ctx, count);
+ for (i = 0; i < count; i++) {
+ acpigen_write_package(ctx, 4);
+ acpigen_write_integer(ctx, info[i].type);
+ acpigen_write_integer(ctx, info[i].flags);
+ acpigen_write_integer(ctx, info[i].gpio_num);
+ acpigen_write_string(ctx, info[i].linux_name);
+ acpigen_pop_len(ctx);
+ }
+
+ acpigen_pop_len(ctx);
+ acpigen_pop_len(ctx);
+
+ return 0;
+}
+
+static int coral_write_acpi_tables(const struct udevice *dev,
+ struct acpi_ctx *ctx)
+{
+ /* Add NHLT here */
+ return 0;
+}
+
+struct acpi_ops coral_acpi_ops = {
+ .write_tables = coral_write_acpi_tables,
+ .inject_dsdt = chromeos_acpi_gpio_generate,
+};
+
+static const struct udevice_id coral_ids[] = {
+ { .compatible = "google,coral" },
+ { }
+};
+
+U_BOOT_DRIVER(coral_drv) = {
+ .name = "coral",
+ .id = UCLASS_BOARD,
+ .of_match = coral_ids,
+ acpi_ops_ptr(&coral_acpi_ops)
+};
diff --git a/board/google/chromebook_coral/dsdt.asl b/board/google/chromebook_coral/dsdt.asl
new file mode 100644
index 0000000000..c74f4145bf
--- /dev/null
+++ b/board/google/chromebook_coral/dsdt.asl
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Google Inc.
+ */
+
+#include "variant_ec.h"
+#include "variant_gpio.h"
+#include <acpi_table.h>
+#include <asm/acpi/global_nvs.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ /* global NVS and variables */
+ #include <asm/arch/acpi/globalnvs.asl>
+
+ /* CPU */
+ #include <asm/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <asm/arch/acpi/northbridge.asl>
+ #include <asm/arch/acpi/southbridge.asl>
+ #include <asm/arch/acpi/pch_hda.asl>
+ }
+ }
+
+ /* Chrome OS specific */
+ #include <asm/acpi/chromeos.asl>
+
+ /* Chipset specific sleep states */
+ #include <asm/acpi/sleepstates.asl>
+
+ /* Chrome OS Embedded Controller */
+ Scope (\_SB.PCI0.LPCB)
+ {
+ /* ACPI code for EC SuperIO functions */
+ #include <asm/acpi/cros_ec/superio.asl>
+ /* ACPI code for EC functions */
+ #include <asm/acpi/cros_ec/ec.asl>
+ }
+
+ /* Dynamic Platform Thermal Framework */
+ Scope (\_SB)
+ {
+ /* Per board variant specific definitions. */
+ #include "variant_dptf.asl"
+ /* Include soc specific DPTF changes */
+ #include <asm/arch/acpi/dptf.asl>
+ /* Include common dptf ASL files */
+ #include <asm/acpi/dptf/dptf.asl>
+ }
+}
diff --git a/board/google/chromebook_coral/variant_dptf.asl b/board/google/chromebook_coral/variant_dptf.asl
new file mode 100644
index 0000000000..943ebeaac2
--- /dev/null
+++ b/board/google/chromebook_coral/variant_dptf.asl
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Google Inc.
+ */
+
+#include "baseboard_dptf.asl"
diff --git a/board/google/chromebook_coral/variant_ec.h b/board/google/chromebook_coral/variant_ec.h
new file mode 100644
index 0000000000..7d5e1a674c
--- /dev/null
+++ b/board/google/chromebook_coral/variant_ec.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+/*
+ * Taken from coreboot file of the same name
+ */
+
+#ifndef VARIANT_EC_H
+#define VARIANT_EC_H
+
+#include "variant_gpio.h"
+#include <ec_commands.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) | \
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
+
+#define EC_ENABLE_TBMC_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+#endif
diff --git a/board/google/chromebook_coral/variant_gpio.h b/board/google/chromebook_coral/variant_gpio.h
new file mode 100644
index 0000000000..f516d88be5
--- /dev/null
+++ b/board/google/chromebook_coral/variant_gpio.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ *
+ * Taken from coreboot file of the same name
+ */
+
+#ifndef BASEBOARD_GPIO_H
+#define BASEBOARD_GPIO_H
+
+#include <asm/arch/gpio.h>
+#include <ec_commands.h>
+
+/*
+ * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
+ * which is North community
+ */
+#define EC_SCI_GPI GPE0_DW1_11
+
+/* EC SMI */
+#define EC_SMI_GPI GPIO_49
+
+/*
+ * On lidopen/lidclose GPIO_22 from North Community gets toggled and
+ * is used in _PRW to wake up device from sleep. GPIO_22 maps to
+ * group GPIO_GPE_N_31_0 and the pad is configured as SCI with
+ * EDGE_SINGLE and INVERT.
+ */
+#define GPE_EC_WAKE GPE0_DW1_22
+
+/* Write Protect and indication if EC is in RW code. */
+#define GPIO_PCH_WP GPIO_75
+#define GPIO_EC_IN_RW GPIO_41
+/* Determine if board is in final shipping mode. */
+#define GPIO_SHIP_MODE GPIO_10
+
+/* Memory SKU GPIOs. */
+#define MEM_CONFIG3 GPIO_45
+#define MEM_CONFIG2 GPIO_38
+#define MEM_CONFIG1 GPIO_102
+#define MEM_CONFIG0 GPIO_101
+
+/* DMIC_CONFIG_PIN: High for 1-DMIC and low for 4-DMIC's */
+#define DMIC_CONFIG_PIN GPIO_17
+
+#ifndef __ASSEMBLY__
+
+enum cros_gpio_t {
+ CROS_GPIO_REC = 1, /* Recovery */
+
+ /* Developer; * deprecated (chromium:942901) */
+ CROS_GPIO_DEPRECATED_DEV = 2,
+ CROS_GPIO_WP = 3, /* Write Protect */
+ CROS_GPIO_PE = 4, /* Phase enforcement for final product */
+
+ CROS_GPIO_ACTIVE_LOW = 0,
+ CROS_GPIO_ACTIVE_HIGH = 1,
+
+ CROS_GPIO_VIRTUAL = -1,
+};
+#endif
+
+#endif /* BASEBOARD_GPIO_H */
--
2.25.0.341.g760bfbb309-goog
More information about the U-Boot
mailing list