[PATCH 081/108] x86: apl: Update iomap for ACPI
Simon Glass
sjg at chromium.org
Mon Jan 27 06:06:28 CET 2020
Add some more definitions to the iomap. These will be used by
ACPI-generation code as well as the device tree.
Signed-off-by: Simon Glass <sjg at chromium.org>
---
arch/x86/include/asm/arch-apollolake/iomap.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h b/arch/x86/include/asm/arch-apollolake/iomap.h
index 4ce1017055..d12268c825 100644
--- a/arch/x86/include/asm/arch-apollolake/iomap.h
+++ b/arch/x86/include/asm/arch-apollolake/iomap.h
@@ -11,11 +11,28 @@
/* Put p2sb at 0xd0000000 in TPL */
#define IOMAP_P2SB_BAR 0xd0000000
+#define IOMAP_P2SB_SIZE 0x10000000
#define IOMAP_SPI_BASE 0xfe010000
#define IOMAP_ACPI_BASE 0x400
#define IOMAP_ACPI_SIZE 0x100
+#define ACPI_BASE_ADDRESS IOMAP_ACPI_BASE
+
+#define PMC_BAR0 0xfe042000
+
+#define MCH_BASE_ADDRESS 0xfed10000
+#define MCH_SIZE 0x8000
+#ifdef __ACPI__
+#define HPET_BASE_ADDRESS 0xfed00000
+
+#define PMC_BAR0 0xfe042000
+
+#define SRAM_BASE_0 0xfe900000
+#define SRAM_SIZE_0 (8 * KiB)
+#define SRAM_BASE_2 0xfe902000
+#define SRAM_SIZE_2 (4 * KiB)
+#endif
/*
* Use UART2. To use UART1 you need to set '2' to '1', change device tree serial
--
2.25.0.341.g760bfbb309-goog
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