[PATCH v5 06/12] arm: mvebu: clearfog: Add SATA mode flags

[Baruch Siach]

Hi Joel,

On Mon, Jan 27, 2020 at 01:01:50PM -0700, Joel Johnson wrote:
> The mPCIe slots on ClearFog Pro and ClearFog Base may be alternately
> configured for SATA usage.
> 
> Signed-off-by: Joel Johnson <mrjoel at lixil.net>
> 
> ---
> 
> v2 changes:
>   - fixed help indentation
> v3 changes:
>   - none
> v4 changes:
>   - adjust static SerDes configuration at runtime instead of #ifdef
>   - add setting of swap_rx for SATA (as yet untested on hardware)
> v5 changes:
>   - make independent of runtime detection
> 
> ---
>  board/solidrun/clearfog/Kconfig    | 17 +++++++++++++++++
>  board/solidrun/clearfog/clearfog.c | 15 +++++++++++++++
>  2 files changed, 32 insertions(+)
> 
> diff --git a/board/solidrun/clearfog/Kconfig b/board/solidrun/clearfog/Kconfig
> index c910e17093..44224d903d 100644
> --- a/board/solidrun/clearfog/Kconfig
> +++ b/board/solidrun/clearfog/Kconfig
> @@ -15,6 +15,23 @@ config TARGET_CLEARFOG_BASE
>  	  detection via additional EEPROM hardware. This option enables selecting
>  	  the Base variant for older hardware revisions.
>  
> +config CLEARFOG_CON3_SATA
> +	bool "Use CON3 slot in SATA mode"
> +	help
> +	  Use the CON3 port with SATA protocol instead of the default PCIe.
> +	  The ClearFog port allows usage of either mSATA or miniPCIe
> +	  modules, but the desired protocol must be configured at build
> +	  time since it affects the SerDes topology layout.
> +
> +config CLEARFOG_CON2_SATA
> +	bool "Use CON2 slot in SATA mode"
> +	depends on !TARGET_CLEARFOG_BASE
> +	help
> +	  Use the CON2 port with SATA protocol instead of the default PCIe.
> +	  The ClearFog port allows usage of either mSATA or miniPCIe
> +	  modules, but the desired protocol must be configured at build
> +	  time since it affects the SerDes topology layout.
> +
>  config CLEARFOG_SFP_25GB
>  	bool "Enable 2.5 Gbps mode for SFP"
>  	help
> diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
> index 064ce4e520..f650e2b40e 100644
> --- a/board/solidrun/clearfog/clearfog.c
> +++ b/board/solidrun/clearfog/clearfog.c
> @@ -67,6 +67,21 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
>  	if (IS_ENABLED(CONFIG_CLEARFOG_SFP_25GB))
>  		board_serdes_map[5].serdes_speed = SERDES_SPEED_3_125_GBPS;
>  
> +	if (IS_ENABLED(CONFIG_CLEARFOG_CON2_SATA) &&
> +	    !IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE)) {

This second condition looks redundant. CONFIG_CLEARFOG_CON2_SATA already 
depends on !CONFIG_TARGET_CLEARFOG_BASE at the Kconfig level above.

Looks good to me otherwise.

Have you had a chance to test mSATA?

> +		board_serdes_map[4].serdes_type = SATA2;
> +		board_serdes_map[4].serdes_speed = SERDES_SPEED_3_GBPS;
> +		board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
> +		board_serdes_map[4].swap_rx = 1;
> +	}
> +
> +	if (IS_ENABLED(CONFIG_CLEARFOG_CON3_SATA)) {
> +		board_serdes_map[2].serdes_type = SATA1;
> +		board_serdes_map[2].serdes_speed = SERDES_SPEED_3_GBPS;
> +		board_serdes_map[2].serdes_mode = SERDES_DEFAULT_MODE;
> +		board_serdes_map[2].swap_rx = 1;
> +	}
> +
>  	/* Apply runtime detection changes */
>  	if (sr_product_is(&cf_tlv_data, "Clearfog GTR")) {
>  		board_serdes_map[0].serdes_type = PEX0;

baruch

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