[PATCH v2 14/21] ARM: dts: imxrt1050: add dtsi file
Lukasz Majewski
lukma at denx.de
Tue Jan 28 09:31:04 CET 2020
Hi Giulio,
> Add dtsi file for i.MXRT1050.
>
Please add information from where this code was ported (as I've pointed
out in other mails).
Also a tip:
To avoid extra dtsi maintenance burden, there are u-boot*.dtsi files
(in e.g. arch/arm/dts/) which add extra properties (U-boot specific).
In that way "original" dtsi (from e.g. Linux) are kept separated from
U-Boot adjustments).
> Signed-off-by: Giulio Benetti <giulio.benetti at benettiengineering.com>
> ---
> arch/arm/dts/imxrt1050.dtsi | 146 +++
> include/dt-bindings/pinctrl/pins-imxrt1050.h | 993
> +++++++++++++++++++ 2 files changed, 1139 insertions(+)
> create mode 100644 arch/arm/dts/imxrt1050.dtsi
> create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1050.h
>
> diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
> new file mode 100644
> index 0000000000..b1d98e6feb
> --- /dev/null
> +++ b/arch/arm/dts/imxrt1050.dtsi
> @@ -0,0 +1,146 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti at benettiengineering.com>
> + */
> +
> +#include "skeleton.dtsi"
> +#include "armv7-m.dtsi"
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/imxrt1050-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/memory/imxrt-sdram.h>
> +
> +/ {
> + aliases {
> + gpio0 = &gpio1;
> + gpio1 = &gpio2;
> + gpio2 = &gpio3;
> + gpio3 = &gpio4;
> + gpio4 = &gpio5;
> + mmc0 = &usdhc1;
> + serial0 = &lpuart1;
> + };
> +
> + clocks {
> + u-boot,dm-spl;
> +
> + osc {
> + u-boot,dm-spl;
> + compatible = "fsl,imx-osc", "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + };
> + };
> +
> + soc {
> + u-boot,dm-spl;
> +
> + semc: semc at 402f0000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-semc";
> + reg = <0x402f0000 0x4000>;
> + clocks = <&clks IMXRT1050_CLK_SEMC>;
> + pinctrl-0 = <&pinctrl_semc>;
> + pinctrl-names = "default";
> + status = "okay";
> + };
> +
> + lpuart1: serial at 40184000 {
> + compatible = "fsl,imxrt-lpuart";
> + reg = <0x40184000 0x4000>;
> + interrupts = <GIC_SPI 20
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMXRT1050_CLK_LPUART1>;
> + clock-names = "per";
> + status = "disabled";
> + };
> +
> + iomuxc: iomuxc at 401f8000 {
> + compatible = "fsl,imxrt-iomuxc";
> + reg = <0x401f8000 0x4000>;
> + fsl,mux_mask = <0x7>;
> + };
> +
> + clks: ccm at 400fc000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt1050-ccm";
> + reg = <0x400fc000 0x4000>;
> + interrupts = <GIC_SPI 95
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 96
> IRQ_TYPE_LEVEL_HIGH>;
> + #clock-cells = <1>;
> + };
> +
> + usdhc1: usdhc at 402c0000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-usdhc";
> + reg = <0x402c0000 0x10000>;
> + interrupts = <GIC_SPI 110
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMXRT1050_CLK_USDHC1>;
> + clock-names = "per";
> + bus-width = <4>;
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step= <2>;
> + status = "disabled";
> + };
> +
> + gpio1: gpio at 401b8000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> + reg = <0x401b8000 0x4000>;
> + interrupts = <GIC_SPI 80
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 81
> IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio2: gpio at 401bc000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> + reg = <0x401bc000 0x4000>;
> + interrupts = <GIC_SPI 82
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio3: gpio at 401c0000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> + reg = <0x401c0000 0x4000>;
> + interrupts = <GIC_SPI 84
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio4: gpio at 401c4000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> + reg = <0x401c4000 0x4000>;
> + interrupts = <GIC_SPI 86
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 87
> IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio5: gpio at 400c0000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> + reg = <0x400c0000 0x4000>;
> + interrupts = <GIC_SPI 88
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +};
> diff --git a/include/dt-bindings/pinctrl/pins-imxrt1050.h
> b/include/dt-bindings/pinctrl/pins-imxrt1050.h new file mode 100644
> index 0000000000..a29031ab3d
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/pins-imxrt1050.h
> @@ -0,0 +1,993 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti at benettiengineering.com>
> + */
> +
> +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
> +#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
> +
> +#define IMX_PAD_SION 0x40000000
> +
> +/*
> + * The pin function ID is a tuple of
> + * <mux_reg conf_reg input_reg mux_mode input_val>
> + */
> +
> +#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
> 0x014 0x204 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A
> 0x014 0x204 0x494 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK
> 0x014 0x204 0x500 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2
> 0x014 0x204 0x60C 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00
> 0x014 0x204 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00
> 0x014 0x204 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
> 0x018 0x208 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B
> 0x018 0x208 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0
> 0x018 0x208 0x4FC 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3
> 0x018 0x208 0x610 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01
> 0x018 0x208 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01
> 0x018 0x208 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
> 0x01C 0x20C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A
> 0x01C 0x20C 0x498 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO
> 0x01C 0x20C 0x508 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4
> 0x01C 0x20C 0x614 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02
> 0x01C 0x20C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02
> 0x01C 0x20C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
> 0x020 0x210 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B
> 0x020 0x210 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI
> 0x020 0x210 0x504 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5
> 0x020 0x210 0x618 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03
> 0x020 0x210 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03
> 0x020 0x210 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
> 0x024 0x214 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A
> 0x024 0x214 0x49C 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024
> 0x214 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6
> 0x024 0x214 0x61C 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04
> 0x024 0x214 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04
> 0x024 0x214 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
> 0x028 0x218 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B
> 0x028 0x218 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028
> 0x218 0x5C4 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7
> 0x028 0x218 0x620 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05
> 0x028 0x218 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05
> 0x028 0x218 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
> 0x02C 0x21C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A
> 0x02C 0x21C 0x478 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C
> 0x21C 0x5C0 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8
> 0x02C 0x21C 0x624 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06
> 0x02C 0x21C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06
> 0x02C 0x21C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
> 0x030 0x220 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B
> 0x030 0x220 0x488 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK
> 0x030 0x220 0x5B0 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9
> 0x030 0x220 0x628 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07
> 0x030 0x220 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07
> 0x030 0x220 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
> 0x034 0x224 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A
> 0x034 0x224 0x47C 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034
> 0x224 0x5B8 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034
> 0x224 0x62C 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08
> 0x034 0x224 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08
> 0x034 0x224 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
> 0x038 0x228 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B
> 0x038 0x228 0x48C 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038
> 0x228 0x5BC 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX
> 0x038 0x228 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09
> 0x038 0x228 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09
> 0x038 0x228 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
> 0x03C 0x22C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A
> 0x03C 0x22C 0x480 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C
> 0x22C 0x5B4 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX
> 0x03C 0x22C 0x450 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10
> 0x03C 0x22C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10
> 0x03C 0x22C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
> 0x040 0x230 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B
> 0x040 0x230 0x490 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA
> 0x040 0x230 0x4E8 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B
> 0x040 0x230 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11
> 0x040 0x230 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11
> 0x040 0x230 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
> 0x044 0x234 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044
> 0x234 0x640 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL
> 0x044 0x234 0x4E4 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP
> 0x044 0x234 0x5D8 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A
> 0x044 0x234 0x454 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12
> 0x044 0x234 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
> 0x048 0x238 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048
> 0x238 0x650 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD
> 0x048 0x238 0x53C 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT
> 0x048 0x238 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B
> 0x048 0x238 0x464 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13
> 0x048 0x238 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
> 0x04C 0x23C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C
> 0x23C 0x654 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD
> 0x04C 0x23C 0x538 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT
> 0x04C 0x23C 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1
> 0x04C 0x23C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14
> 0x04C 0x23C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
> 0x050 0x240 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050
> 0x240 0x634 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B
> 0x050 0x240 0x534 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT
> 0x050 0x240 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0
> 0x050 0x240 0x57C 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15
> 0x050 0x240 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
> 0x054 0x244 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054
> 0x244 0x658 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B
> 0x054 0x244 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN
> 0x054 0x244 0x5C8 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1
> 0x054 0x244 0x580 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16
> 0x054 0x244 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
> 0x058 0x248 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A
> 0x058 0x248 0x4A0 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B
> 0x058 0x248 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX
> 0x058 0x248 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2
> 0x058 0x248 0x584 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17
> 0x058 0x248 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
> 0x05C 0x24C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B
> 0x05C 0x24C 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B
> 0x05C 0x24C 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX
> 0x05C 0x24C 0x44C 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3
> 0x05C 0x24C 0x588 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18
> 0x05C 0x24C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL
> 0x05C 0x24C 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
> 0x060 0x250 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A
> 0x060 0x250 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD
> 0x060 0x250 0x544 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01
> 0x060 0x250 0x438 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0
> 0x060 0x250 0x56C 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19
> 0x060 0x250 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5
> 0x060 0x250 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
> 0x064 0x254 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B
> 0x064 0x254 0x484 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD
> 0x064 0x254 0x540 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00
> 0x064 0x254 0x434 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0
> 0x064 0x254 0x570 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20
> 0x064 0x254 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
> 0x068 0x258 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A
> 0x068 0x258 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA
> 0x068 0x258 0x4E0 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01
> 0x068 0x258 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2
> 0x068 0x258 0x574 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21
> 0x068 0x258 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
> 0x06C 0x25C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B
> 0x06C 0x25C 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL
> 0x06C 0x25C 0x4DC 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00
> 0x06C 0x25C 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3
> 0x06C 0x25C 0x578 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22
> 0x06C 0x25C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
> 0x070 0x260 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A
> 0x070 0x260 0x458 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD
> 0x070 0x260 0x54C 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN
> 0x070 0x260 0x43C 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2
> 0x070 0x260 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23
> 0x070 0x260 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
> 0x074 0x264 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B
> 0x074 0x264 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD
> 0x074 0x264 0x548 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN
> 0x074 0x264 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1
> 0x074 0x264 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24
> 0x074 0x264 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
> 0x078 0x268 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A
> 0x078 0x268 0x45C 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD
> 0x078 0x268 0x554 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK
> 0x078 0x268 0x448 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078
> 0x268 0x42C 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25
> 0x078 0x268 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
> 0x07C 0x26C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B
> 0x07C 0x26C 0x46C 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD
> 0x07C 0x26C 0x550 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER
> 0x07C 0x26C 0x440 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12
> 0x07C 0x26C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26
> 0x07C 0x26C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
> 0x080 0x270 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A
> 0x080 0x270 0x460 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B
> 0x080 0x270 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK
> 0x080 0x270 0x4F0 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13
> 0x080 0x270 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27
> 0x080 0x270 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
> 0x084 0x274 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B
> 0x084 0x274 0x470 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B
> 0x084 0x274 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO
> 0x084 0x274 0x4F8 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14
> 0x084 0x274 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28
> 0x084 0x274 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
> 0x088 0x278 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A
> 0x088 0x278 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B
> 0x088 0x278 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI
> 0x088 0x278 0x4F4 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15
> 0x088 0x278 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29
> 0x088 0x278 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
> 0x08C 0x27C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B
> 0x08C 0x27C 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B
> 0x08C 0x27C 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0
> 0x08C 0x27C 0x4EC 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23
> 0x08C 0x27C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30
> 0x08C 0x27C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
> 0x090 0x280 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A
> 0x090 0x280 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD
> 0x090 0x280 0x55C 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1
> 0x090 0x280 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22
> 0x090 0x280 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31
> 0x090 0x280 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
> 0x094 0x284 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B
> 0x094 0x284 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD
> 0x094 0x284 0x558 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY
> 0x094 0x284 0x3FC 0x3 0x4 +#define
> MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21
> 0x094 0x284 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18
> 0x094 0x284 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
> 0x098 0x288 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A
> 0x098 0x288 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B
> 0x098 0x288 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098
> 0x288 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20
> 0x098 0x288 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19
> 0x098 0x288 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
> 0x09C 0x28C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B
> 0x09C 0x28C 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT
> 0x09C 0x28C 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C
> 0x28C 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19
> 0x09C 0x28C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20
> 0x09C 0x28C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
> 0x0A0 0x290 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0
> 0x290 0x630 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1
> 0x0A0 0x290 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0
> 0x290 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18
> 0x0A0 0x290 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21
> 0x0A0 0x290 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B
> 0x0A0 0x290 0x5D4 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
> 0x0A4 0x294 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4
> 0x294 0x638 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2
> 0x0A4 0x294 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4
> 0x294 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17
> 0x0A4 0x294 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22
> 0x0A4 0x294 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP
> 0x0A4 0x294 0x5D8 0x6 0x1 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
> 0x0A8 0x298 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8
> 0x298 0x63C 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3
> 0x0A8 0x298 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK
> 0x0A8 0x298 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16
> 0x0A8 0x298 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23
> 0x0A8 0x298 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP
> 0x0A8 0x298 0x608 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
> 0x0AC 0x29C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A
> 0x0AC 0x29C 0x454 0x1 0x2 +#define
> MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD
> 0x0AC 0x29C 0x564 0x2 0x2 +#define
> MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC
> 0x29C 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD
> 0x0AC 0x29C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24
> 0x0AC 0x29C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT
> 0x0AC 0x29C 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
> 0x0B0 0x2A0 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B
> 0x0B0 0x2A0 0x464 0x1 0x2 +#define
> MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD
> 0x0B0 0x2A0 0x560 0x2 0x2 +#define
> MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0
> 0x2A0 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B
> 0x0B0 0x2A0 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25
> 0x0B0 0x2A0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B
> 0x0B0 0x2A0 0x5E0 0x6 0x1 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY
> 0x0B4 0x2A4 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2
> 0x0B4 0x2A4 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2
> 0x0B4 0x2A4 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC
> 0x0B4 0x2A4 0x5CC 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC
> 0x0B4 0x2A4 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26
> 0x0B4 0x2A4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B
> 0x0B4 0x2A4 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0
> 0x0B8 0x2A8 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1
> 0x0B8 0x2A8 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3
> 0x0B8 0x2A8 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8
> 0x2A8 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO
> 0x0B8 0x2A8 0x430 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27
> 0x0B8 0x2A8 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT
> 0x0B8 0x2A8 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A
> 0x0BC 0x2AC 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14
> 0x0BC 0x2AC 0x644 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K
> 0x0BC 0x2AC 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID
> 0x0BC 0x2AC 0x3F8 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS
> 0x0BC 0x2AC 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC
> 0x2AC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B
> 0x0BC 0x2AC 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC
> 0x2AC 0x510 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B
> 0x0C0 0x2B0 0x484 0x0 0x2 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15
> 0x0C0 0x2B0 0x648 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M
> 0x0C0 0x2B0 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID
> 0x0C0 0x2B0 0x3F4 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS
> 0x0C0 0x2B0 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0
> 0x2B0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B
> 0x0C0 0x2B0 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0
> 0x2B0 0x518 0x7 0x1 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX
> 0x0C4 0x2B4 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16
> 0x0C4 0x2B4 0x64C 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD
> 0x0C4 0x2B4 0x554 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR
> 0x0C4 0x2B4 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X
> 0x0C4 0x2B4 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4
> 0x2B4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ
> 0x0C4 0x2B4 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4
> 0x2B4 0x514 0x7 0x1 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX
> 0x0C8 0x2B8 0x450 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17
> 0x0C8 0x2B8 0x62C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD
> 0x0C8 0x2B8 0x550 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC
> 0x0C8 0x2B8 0x5D0 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X
> 0x0C8 0x2B8 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8
> 0x2B8 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M
> 0x0C8 0x2B8 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0
> 0x0C8 0x2B8 0x50C 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00
> 0x0CC 0x2BC 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT
> 0x0CC 0x2BC 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03
> 0x0CC 0x2BC 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC
> 0x0CC 0x2BC 0x5C4 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC
> 0x2BC 0x41C 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC
> 0x2BC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00
> 0x0CC 0x2BC 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1
> 0x0CC 0x2BC 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01
> 0x0D0 0x2C0 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT
> 0x0D0 0x2C0 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02
> 0x0D0 0x2C0 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK
> 0x0D0 0x2C0 0x5C0 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0
> 0x2C0 0x418 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0
> 0x2C0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17
> 0x0D0 0x2C0 0x62C 0x6 0x2 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2
> 0x0D0 0x2C0 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS
> 0x0D4 0x2C4 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1
> 0x0D4 0x2C4 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK
> 0x0D4 0x2C4 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK
> 0x0D4 0x2C4 0x5B4 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4
> 0x2C4 0x414 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4
> 0x2C4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18
> 0x0D4 0x2C4 0x630 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3
> 0x0D4 0x2C4 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK
> 0x0D8 0x2C8 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2
> 0x0D8 0x2C8 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8
> 0x2C8 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC
> 0x0D8 0x2C8 0x5BC 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8
> 0x2C8 0x410 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8
> 0x2C8 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19
> 0x0D8 0x2C8 0x654 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT
> 0x0D8 0x2C8 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD
> 0x0DC 0x2CC 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3
> 0x0DC 0x2CC 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03
> 0x0DC 0x2CC 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA
> 0x0DC 0x2CC 0x5B8 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC
> 0x2CC 0x40C 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC
> 0x2CC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20
> 0x0DC 0x2CC 0x634 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN
> 0x0DC 0x2CC 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI
> 0x0E0 0x2D0 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A
> 0x0E0 0x2D0 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02
> 0x0E0 0x2D0 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA
> 0x0E0 0x2D0 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0
> 0x2D0 0x408 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0
> 0x2D0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21
> 0x0E0 0x2D0 0x658 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK
> 0x0E0 0x2D0 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO
> 0x0E4 0x2D4 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A
> 0x0E4 0x2D4 0x454 0x1 0x3 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS
> 0x0E4 0x2D4 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK
> 0x0E4 0x2D4 0x5B0 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4
> 0x2D4 0x404 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4
> 0x2D4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22
> 0x0E4 0x2D4 0x638 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT
> 0x0E4 0x2D4 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8
> 0x2D8 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B
> 0x0E8 0x2D8 0x464 0x1 0x3 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL
> 0x0E8 0x2D8 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B
> 0x0E8 0x2D8 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8
> 0x2D8 0x400 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8
> 0x2D8 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23
> 0x0E8 0x2D8 0x63C 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN
> 0x0E8 0x2D8 0x444 0x7 0x1 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC
> 0x2DC 0x4E4 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY
> 0x0EC 0x2DC 0x3FC 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
> 0x0EC 0x2DC 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B
> 0x0EC 0x2DC 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X
> 0x0EC 0x2DC 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC
> 0x2DC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT
> 0x0EC 0x2DC 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI
> 0x0EC 0x2DC 0x568 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0
> 0x2E0 0x4E8 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK
> 0x0F0 0x2E0 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
> 0x0F0 0x2E0 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B
> 0x0F0 0x2E0 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X
> 0x0F0 0x2E0 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0
> 0x2E0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN
> 0x0F0 0x2E0 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M
> 0x0F0 0x2E0 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC
> 0x0F4 0x2E4 0x5CC 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24
> 0x0F4 0x2E4 0x640 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B
> 0x0F4 0x2E4 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT
> 0x0F4 0x2E4 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC
> 0x0F4 0x2E4 0x428 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4
> 0x2E4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX
> 0x0F4 0x2E4 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR
> 0x0F8 0x2E8 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25
> 0x0F8 0x2E8 0x650 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B
> 0x0F8 0x2E8 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN
> 0x0F8 0x2E8 0x444 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC
> 0x0F8 0x2E8 0x420 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8
> 0x2E8 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX
> 0x0F8 0x2E8 0x450 0x6 0x2 +#define
> MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB
> 0x0F8 0x2E8 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID
> 0x0FC 0x2EC 0x3F8 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0
> 0x0FC 0x2EC 0x57C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B
> 0x0FC 0x2EC 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC
> 0x2EC 0x4CC 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B
> 0x0FC 0x2EC 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC
> 0x2EC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP
> 0x0FC 0x2EC 0x5D8 0x6 0x2 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07
> 0x0FC 0x2EC 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR
> 0x100 0x2F0 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1
> 0x100 0x2F0 0x580 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B
> 0x100 0x2F0 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100
> 0x2F0 0x4D0 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY
> 0x100 0x2F0 0x3FC 0x4 0x2 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100
> 0x2F0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT
> 0x100 0x2F0 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07
> 0x100 0x2F0 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID
> 0x104 0x2F4 0x3F4 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2
> 0x104 0x2F4 0x584 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD
> 0x104 0x2F4 0x530 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT
> 0x104 0x2F4 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT
> 0x104 0x2F4 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104
> 0x2F4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B
> 0x104 0x2F4 0x5D4 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06
> 0x104 0x2F4 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC
> 0x108 0x2F8 0x5D0 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3
> 0x108 0x2F8 0x588 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD
> 0x108 0x2F8 0x52C 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN
> 0x108 0x2F8 0x5C8 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN
> 0x108 0x2F8 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108
> 0x2F8 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B
> 0x108 0x2F8 0x5E0 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06
> 0x108 0x2F8 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3
> 0x10C 0x2FC 0x4C4 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC
> 0x10C 0x2FC 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B
> 0x10C 0x2FC 0x534 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK
> 0x10C 0x2FC 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C
> 0x2FC 0x424 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C
> 0x2FC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0
> 0x10C 0x2FC 0x5E8 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05
> 0x10C 0x2FC 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2
> 0x110 0x300 0x4C0 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO
> 0x110 0x300 0x430 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B
> 0x110 0x300 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT
> 0x110 0x300 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK
> 0x110 0x300 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110
> 0x300 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1
> 0x110 0x300 0x5EC 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05
> 0x110 0x300 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1
> 0x114 0x304 0x4BC 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114
> 0x304 0x4E0 0x1 0x2 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD
> 0x114 0x304 0x53C 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114
> 0x304 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC
> 0x114 0x304 0x428 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114
> 0x304 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2
> 0x114 0x304 0x5F0 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04
> 0x114 0x304 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0
> 0x118 0x308 0x4B8 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118
> 0x308 0x4DC 0x1 0x2 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD
> 0x118 0x308 0x538 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK
> 0x118 0x308 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC
> 0x118 0x308 0x420 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118
> 0x308 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3
> 0x118 0x308 0x5F4 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04
> 0x118 0x308 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B
> 0x11C 0x30C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A
> 0x11C 0x30C 0x494 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX
> 0x11C 0x30C 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY
> 0x11C 0x30C 0x3FC 0x3 0x3 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C
> 0x30C 0x41C 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C
> 0x30C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C
> 0x30C 0x5E4 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03
> 0x11C 0x30C 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS
> 0x120 0x310 0x4A4 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A
> 0x120 0x310 0x498 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX
> 0x120 0x310 0x44C 0x2 0x2 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK
> 0x120 0x310 0x58C 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120
> 0x310 0x418 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120
> 0x310 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120
> 0x310 0x5DC 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03
> 0x120 0x310 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3
> 0x124 0x314 0x4B4 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B
> 0x124 0x314 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD
> 0x124 0x314 0x564 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC
> 0x124 0x314 0x5A4 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124
> 0x314 0x414 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124
> 0x314 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP
> 0x124 0x314 0x608 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02
> 0x124 0x314 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2
> 0x128 0x318 0x4B0 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B
> 0x128 0x318 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD
> 0x128 0x318 0x560 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK
> 0x128 0x318 0x590 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128
> 0x318 0x410 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128
> 0x318 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B
> 0x128 0x318 0x000 0x6 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02
> 0x128 0x318 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1
> 0x12C 0x31C 0x4AC 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT
> 0x12C 0x31C 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0
> 0x12C 0x31C 0x50C 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00
> 0x12C 0x31C 0x594 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C
> 0x31C 0x40C 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C
> 0x31C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4
> 0x12C 0x31C 0x5F8 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01
> 0x12C 0x31C 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0
> 0x130 0x320 0x4A8 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT
> 0x130 0x320 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130
> 0x320 0x514 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00
> 0x130 0x320 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130
> 0x320 0x408 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130
> 0x320 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5
> 0x130 0x320 0x5FC 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01
> 0x130 0x320 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK
> 0x134 0x324 0x4C8 0x0 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT
> 0x134 0x324 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134
> 0x324 0x518 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK
> 0x134 0x324 0x5A8 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134
> 0x324 0x404 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134
> 0x324 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6
> 0x134 0x324 0x600 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00
> 0x134 0x324 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B
> 0x138 0x328 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT
> 0x138 0x328 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138
> 0x328 0x510 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC
> 0x138 0x328 0x5AC 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138
> 0x328 0x400 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138
> 0x328 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7
> 0x138 0x328 0x604 0x6 0x1 +#define
> MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00
> 0x138 0x328 0x000 0x7 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK
> 0x13C 0x32C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0
> 0x13C 0x32C 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT
> 0x13C 0x32C 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0
> 0x13C 0x32C 0x51C 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00
> 0x13C 0x32C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00
> 0x13C 0x32C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1
> 0x13C 0x32C 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE
> 0x140 0x330 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1
> 0x140 0x330 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT
> 0x140 0x330 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI
> 0x140 0x330 0x524 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01
> 0x140 0x330 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01
> 0x140 0x330 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2
> 0x140 0x330 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC
> 0x144 0x334 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2
> 0x144 0x334 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX
> 0x144 0x334 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO
> 0x144 0x334 0x528 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02
> 0x144 0x334 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02
> 0x144 0x334 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3
> 0x144 0x334 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC
> 0x148 0x338 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0
> 0x148 0x338 0x56C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX
> 0x148 0x338 0x44C 0x2 0x3 +#define
> MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK
> 0x148 0x338 0x520 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03
> 0x148 0x338 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03
> 0x148 0x338 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB
> 0x148 0x338 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00
> 0x14C 0x33C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1
> 0x14C 0x33C 0x570 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL
> 0x14C 0x33C 0x4D4 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00
> 0x14C 0x33C 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04
> 0x14C 0x33C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04
> 0x14C 0x33C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00
> 0x14C 0x33C 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01
> 0x150 0x340 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2
> 0x150 0x340 0x574 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA
> 0x150 0x340 0x4D8 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01
> 0x150 0x340 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05
> 0x150 0x340 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05
> 0x150 0x340 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01
> 0x150 0x340 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02
> 0x154 0x344 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0
> 0x154 0x344 0x57C 0x1 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A
> 0x154 0x344 0x478 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02
> 0x154 0x344 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06
> 0x154 0x344 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06
> 0x154 0x344 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02
> 0x154 0x344 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03
> 0x158 0x348 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1
> 0x158 0x348 0x580 0x1 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B
> 0x158 0x348 0x488 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03
> 0x158 0x348 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07
> 0x158 0x348 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07
> 0x158 0x348 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03
> 0x158 0x348 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04
> 0x15C 0x34C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2
> 0x15C 0x34C 0x584 0x1 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A
> 0x15C 0x34C 0x47C 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD
> 0x15C 0x34C 0x53C 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08
> 0x15C 0x34C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08
> 0x15C 0x34C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04
> 0x15C 0x34C 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05
> 0x160 0x350 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0
> 0x160 0x350 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B
> 0x160 0x350 0x48C 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD
> 0x160 0x350 0x538 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09
> 0x160 0x350 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09
> 0x160 0x350 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05
> 0x160 0x350 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06
> 0x164 0x354 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1
> 0x164 0x354 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A
> 0x164 0x354 0x480 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03
> 0x164 0x354 0x598 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10
> 0x164 0x354 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10
> 0x164 0x354 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06
> 0x164 0x354 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07
> 0x168 0x358 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2
> 0x168 0x358 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B
> 0x168 0x358 0x490 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02
> 0x168 0x358 0x59C 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11
> 0x168 0x358 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11
> 0x168 0x358 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07
> 0x168 0x358 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08
> 0x16C 0x35C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10
> 0x16C 0x35C 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C
> 0x35C 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01
> 0x16C 0x35C 0x5A0 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12
> 0x16C 0x35C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12
> 0x16C 0x35C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08
> 0x16C 0x35C 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09
> 0x170 0x360 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11
> 0x170 0x360 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170
> 0x360 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK
> 0x170 0x360 0x58C 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13
> 0x170 0x360 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13
> 0x170 0x360 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09
> 0x170 0x360 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10
> 0x174 0x364 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12
> 0x174 0x364 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV
> 0x174 0x364 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC
> 0x174 0x364 0x5A4 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14
> 0x174 0x364 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14
> 0x174 0x364 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10
> 0x174 0x364 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11
> 0x178 0x368 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13
> 0x178 0x368 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV
> 0x178 0x368 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK
> 0x178 0x368 0x590 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15
> 0x178 0x368 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15
> 0x178 0x368 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11
> 0x178 0x368 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12
> 0x17C 0x36C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14
> 0x17C 0x36C 0x644 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD
> 0x17C 0x36C 0x544 0x2 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00
> 0x17C 0x36C 0x594 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16
> 0x17C 0x36C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16
> 0x17C 0x36C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A
> 0x17C 0x36C 0x454 0x6 0x4 + +#define
> MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13
> 0x180 0x370 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15
> 0x180 0x370 0x648 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD
> 0x180 0x370 0x540 0x2 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00
> 0x180 0x370 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17
> 0x180 0x370 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17
> 0x180 0x370 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B
> 0x180 0x370 0x464 0x6 0x4 + +#define
> MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14
> 0x184 0x374 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16
> 0x184 0x374 0x64C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2
> 0x184 0x374 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK
> 0x184 0x374 0x5A8 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18
> 0x184 0x374 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18
> 0x184 0x374 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A
> 0x184 0x374 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15
> 0x188 0x378 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17
> 0x188 0x378 0x62C 0x1 0x3 +#define
> MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1
> 0x188 0x378 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC
> 0x188 0x378 0x5AC 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19
> 0x188 0x378 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19
> 0x188 0x378 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B
> 0x188 0x378 0x484 0x6 0x3 + +#define
> MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16
> 0x18C 0x37C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0
> 0x18C 0x37C 0x51C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15
> 0x18C 0x37C 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00
> 0x18C 0x37C 0x434 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20
> 0x18C 0x37C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20
> 0x18C 0x37C 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17
> 0x190 0x380 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI
> 0x190 0x380 0x524 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14
> 0x190 0x380 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01
> 0x190 0x380 0x438 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21
> 0x190 0x380 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21
> 0x190 0x380 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18
> 0x194 0x384 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO
> 0x194 0x384 0x528 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13
> 0x194 0x384 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN
> 0x194 0x384 0x43C 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22
> 0x194 0x384 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22
> 0x194 0x384 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19
> 0x198 0x388 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK
> 0x198 0x388 0x520 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12
> 0x198 0x388 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00
> 0x198 0x388 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23
> 0x198 0x388 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23
> 0x198 0x388 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20
> 0x19C 0x38C 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3
> 0x19C 0x38C 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11
> 0x19C 0x38C 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01
> 0x19C 0x38C 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24
> 0x19C 0x38C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24
> 0x19C 0x38C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX
> 0x19C 0x38C 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21
> 0x1A0 0x390 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3
> 0x1A0 0x390 0x578 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10
> 0x1A0 0x390 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN
> 0x1A0 0x390 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25
> 0x1A0 0x390 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25
> 0x1A0 0x390 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX
> 0x1A0 0x390 0x450 0x6 0x3 + +#define
> MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22
> 0x1A4 0x394 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3
> 0x1A4 0x394 0x588 0x1 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00
> 0x1A4 0x394 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK
> 0x1A4 0x394 0x448 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26
> 0x1A4 0x394 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26
> 0x1A4 0x394 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK
> 0x1A4 0x394 0x42C 0x6 0x1 + +#define
> MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23
> 0x1A8 0x398 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3
> 0x1A8 0x398 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01
> 0x1A8 0x398 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER
> 0x1A8 0x398 0x440 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27
> 0x1A8 0x398 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27
> 0x1A8 0x398 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3
> 0x1A8 0x398 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD
> 0x1AC 0x39C 0x54C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK
> 0x1AC 0x39C 0x424 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN
> 0x1AC 0x39C 0x444 0x3 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28
> 0x1AC 0x39C 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28
> 0x1AC 0x39C 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
> 0x1AC 0x39C 0x5D4 0x6 0x2 + +#define
> MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B
> 0x1B0 0x3A0 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD
> 0x1B0 0x3A0 0x548 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC
> 0x1B0 0x3A0 0x428 0x2 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT
> 0x1B0 0x3A0 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29
> 0x1B0 0x3A0 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29
> 0x1B0 0x3A0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP
> 0x1B0 0x3A0 0x5D8 0x6 0x3 + +#define
> MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC
> 0x1B4 0x3A4 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A
> 0x1B4 0x3A4 0x49C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC
> 0x1B4 0x3A4 0x420 0x2 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02
> 0x1B4 0x3A4 0x60C 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30
> 0x1B4 0x3A4 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30
> 0x1B4 0x3A4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
> 0x1B4 0x3A4 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO
> 0x1B8 0x3A8 0x430 0x0 0x2 +#define
> MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A
> 0x1B8 0x3A8 0x4A0 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK
> 0x1B8 0x3A8 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03
> 0x1B8 0x3A8 0x610 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31
> 0x1B8 0x3A8 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31
> 0x1B8 0x3A8 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B
> 0x1B8 0x3A8 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC
> 0x3AC 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A
> 0x1BC 0x3AC 0x458 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC
> 0x3AC 0x4DC 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04
> 0x1BC 0x3AC 0x614 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC
> 0x3AC 0x4F0 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC
> 0x3AC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B
> 0x1BC 0x3AC 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0
> 0x3B0 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B
> 0x1C0 0x3B0 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0
> 0x3B0 0x4E0 0x2 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05
> 0x1C0 0x3B0 0x618 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0
> 0x1C0 0x3B0 0x4EC 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0
> 0x3B0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B
> 0x1C0 0x3B0 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
> 0x1C4 0x3B4 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A
> 0x1C4 0x3B4 0x45C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B
> 0x1C4 0x3B4 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06
> 0x1C4 0x3B4 0x61C 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4
> 0x3B4 0x4F8 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4
> 0x3B4 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
> 0x1C8 0x3B8 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B
> 0x1C8 0x3B8 0x46C 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B
> 0x1C8 0x3B8 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07
> 0x1C8 0x3B8 0x620 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8
> 0x3B8 0x4F4 0x4 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8
> 0x3B8 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
> 0x1CC 0x3BC 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A
> 0x1CC 0x3BC 0x460 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD
> 0x1CC 0x3BC 0x564 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08
> 0x1CC 0x3BC 0x624 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B
> 0x1CC 0x3BC 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC
> 0x3BC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1
> 0x1CC 0x3BC 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
> 0x1D0 0x3C0 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B
> 0x1D0 0x3C0 0x470 0x1 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD
> 0x1D0 0x3C0 0x560 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09
> 0x1D0 0x3C0 0x628 0x3 0x1 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS
> 0x1D0 0x3C0 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0
> 0x3C0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2
> 0x1D0 0x3C0 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3
> 0x1D4 0x3C4 0x5F4 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3
> 0x1D4 0x3C4 0x4C4 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A
> 0x1D4 0x3C4 0x454 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03
> 0x1D4 0x3C4 0x598 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD
> 0x1D4 0x3C4 0x544 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4
> 0x3C4 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2
> 0x1D8 0x3C8 0x5F0 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2
> 0x1D8 0x3C8 0x4C0 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B
> 0x1D8 0x3C8 0x464 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02
> 0x1D8 0x3C8 0x59C 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD
> 0x1D8 0x3C8 0x540 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8
> 0x3C8 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1
> 0x1DC 0x3CC 0x5EC 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1
> 0x1DC 0x3CC 0x4BC 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A
> 0x1DC 0x3CC 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01
> 0x1DC 0x3CC 0x5A0 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX
> 0x1DC 0x3CC 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC
> 0x3CC 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT
> 0x1DC 0x3CC 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0
> 0x1E0 0x3D0 0x5E8 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0
> 0x1E0 0x3D0 0x4B8 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B
> 0x1E0 0x3D0 0x484 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK
> 0x1E0 0x3D0 0x58C 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX
> 0x1E0 0x3D0 0x44C 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0
> 0x3D0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY
> 0x1E0 0x3D0 0x3FC 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4
> 0x3D4 0x5DC 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK
> 0x1E4 0x3D4 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4
> 0x3D4 0x4CC 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC
> 0x1E4 0x3D4 0x5A4 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B
> 0x1E4 0x3D4 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4
> 0x3D4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP
> 0x1E4 0x3D4 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8
> 0x3D8 0x5E4 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS
> 0x1E8 0x3D8 0x4A4 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8
> 0x3D8 0x4D0 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK
> 0x1E8 0x3D8 0x590 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B
> 0x1E8 0x3D8 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8
> 0x3D8 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B
> 0x1EC 0x3DC 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B
> 0x1EC 0x3DC 0x000 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B
> 0x1EC 0x3DC 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00
> 0x1EC 0x3DC 0x594 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0
> 0x1EC 0x3DC 0x4FC 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC
> 0x3DC 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1
> 0x1F0 0x3E0 0x000 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK
> 0x1F0 0x3E0 0x4C8 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B
> 0x1F0 0x3E0 0x000 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00
> 0x1F0 0x3E0 0x000 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0
> 0x3E0 0x500 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0
> 0x3E0 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B
> 0x1F0 0x3E0 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4
> 0x1F4 0x3E4 0x5F8 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0
> 0x1F4 0x3E4 0x4A8 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD
> 0x1F4 0x3E4 0x55C 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK
> 0x1F4 0x3E4 0x5A8 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4
> 0x3E4 0x508 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4
> 0x3E4 0x000 0x5 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2
> 0x1F4 0x3E4 0x000 0x6 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5
> 0x1F8 0x3E8 0x5FC 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1
> 0x1F8 0x3E8 0x4AC 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD
> 0x1F8 0x3E8 0x558 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC
> 0x1F8 0x3E8 0x5AC 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8
> 0x3E8 0x504 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8
> 0x3E8 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6
> 0x1FC 0x3EC 0x600 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2
> 0x1FC 0x3EC 0x4B0 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD
> 0x1FC 0x3EC 0x52C 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC
> 0x3EC 0x4D8 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2
> 0x1FC 0x3EC 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC
> 0x3EC 0x000 0x5 0x0 + +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7
> 0x200 0x3F0 0x604 0x0 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3
> 0x200 0x3F0 0x4B4 0x1 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD
> 0x200 0x3F0 0x530 0x2 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200
> 0x3F0 0x4D4 0x3 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3
> 0x200 0x3F0 0x000 0x4 0x0 +#define
> MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200
> 0x3F0 0x000 0x5 0x0 + +#endif /*
> _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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