[PATCH v2 2/8] dt-bindings: pinctrl: imx8mm: add alternative uart muxings
Marcel Ziswiler
marcel at ziswiler.com
Tue Jan 28 13:38:59 CET 2020
Hi Frieder
On Mon, 2020-01-27 at 09:10 +0000, Schrempf Frieder wrote:
> Hi,
>
> On 26.01.20 04:55, Marcel Ziswiler wrote:
> > From: Max Krummenacher <max.krummenacher at toradex.com>
> >
> > Add alternative UART muxing defines.
> >
> > Signed-off-by: Max Krummenacher <max.krummenacher at toradex.com>
>
> Patch 1/8 and 2/8 in this series change the pin definitions for the
> i.MX8MM so that they deviate from the definitions in the Linux
> kernel.
Yes, I agree. This is not the best approach.
> As Fabio already pointed out for v1, please instead of adding these
> changes, just sync with the definitions in linux-next [1], which
> should
> already contain these additions from what I can see.
We had a thorough look at this and while we first were in doubt this
being correct in linux-next we understand now that it just implements
whatever bad UART notation used in NXP's reference manual [2] (section
16.2.2 External Signals e.g. anybody intimately familiar with UARTs
knows that a DTE vs. DCE TX pin would have different directions [2]).
Anyway, I will adhere to Fabio and your guidance and just sync with
linux-next for a v3.
> Thanks,
> Frieder
Thanks!
Cheers
Marcel
> [1]:
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h
[2] https://www.nxp.com/webapp/Download?colCode=IMX8MMRM
[3] https://en.wikipedia.org/wiki/RS-232#Data_and_control_signals
> > ---
> >
> > Changes in v2:
> > - Fixed some copy-paste errors.
> >
> > arch/arm/dts/imx8mm-pinfunc.h | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm/dts/imx8mm-pinfunc.h b/arch/arm/dts/imx8mm-
> > pinfunc.h
> > index 3e9955566a..e7fac56db3 100644
> > --- a/arch/arm/dts/imx8mm-pinfunc.h
> > +++ b/arch/arm/dts/imx8mm-pinfunc.h
> > @@ -472,21 +472,37 @@
> > #define
> > MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK
> > 0x1D0 0x438 0x000 0x0 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK
> > 0x1D0 0x438 0x000 0x1 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK
> > 0x1D0 0x438 0x4D0 0x2 0x2
> > +#define
> > MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B
> > 0x1D0 0x438 0x000 0x4 0x0
> > +#define
> > MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_RTS_B
> > 0x1D0 0x438 0x4F8 0x4 0x2
> > +#define
> > MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_CTS_B
> > 0x1D0 0x438 0x4F8 0x4 0x2
> > +#define
> > MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B
> > 0x1D0 0x438 0x000 0x4 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29
> > 0x1D0 0x438 0x000 0x5 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1
> > 0x1D0 0x438 0x000 0x7 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0
> > 0x1D4 0x43C 0x000 0x0 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1
> > 0x1D4 0x43C 0x000 0x1 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0
> > 0x1D4 0x43C 0x4D4 0x2 0x2
> > +#define
> > MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B
> > 0x1D4 0x43C 0x4F8 0x4 0x3
> > +#define
> > MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_CTS_B
> > 0x1D4 0x43C 0x000 0x4 0x0
> > +#define
> > MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_RTS_B
> > 0x1D4 0x43C 0x000 0x4 0x0
> > +#define
> > MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B
> > 0x1D4 0x43C 0x4F8 0x4 0x3
> > #define
> > MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30
> > 0x1D4 0x43C 0x000 0x5 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0
> > 0x1D4 0x43C 0x000 0x7 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC
> > 0x1D8 0x440 0x000 0x0 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2
> > 0x1D8 0x440 0x000 0x1 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1
> > 0x1D8 0x440 0x4D8 0x2 0x2
> > +#define
> > MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX
> > 0x1D8 0x440 0x000 0x4 0x0
> > +#define
> > MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_TX
> > 0x1D8 0x440 0x4FC 0x4 0x2
> > +#define
> > MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_RX
> > 0x1D8 0x440 0x4FC 0x4 0x2
> > +#define
> > MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX
> > 0x1D8 0x440 0x000 0x4 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31
> > 0x1D8 0x440 0x000 0x5 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1
> > 0x1D8 0x440 0x000 0x7 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK
> > 0x1DC 0x444 0x000 0x0 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2
> > 0x1DC 0x444 0x000 0x1 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2
> > 0x1DC 0x444 0x4DC 0x2 0x2
> > +#define
> > MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_RX
> > 0x1DC 0x444 0x000 0x4 0x0
> > +#define
> > MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX
> > 0x1DC 0x444 0x4FC 0x4 0x3
> > +#define
> > MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX
> > 0x1DC 0x444 0x4FC 0x4 0x3
> > +#define
> > MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_TX
> > 0x1DC 0x444 0x000 0x4 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0
> > 0x1DC 0x444 0x000 0x5 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2
> > 0x1DC 0x444 0x000 0x7 0x0
> > #define
> > MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0
> > 0x1E0 0x448 0x000 0x0 0x0
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