[PATCH v3 6/6] board: presidio-asic: Add basic G3 engr. development board support

[Tom Rini]

On Thu, Jan 30, 2020 at 05:29:56AM +0000, Alex Nemirovsky wrote:

> Add basic Presidio G3 engineering board support
> 
> Signed-off-by: Alex Nemirovsky <alex.nemirovsky at cortina-access.com>
[snip]
>  create mode 100644 arch/arm/dts/ca-presidio-engboard.dts

What is the status of upstreaming this file to Linux?

[snip]
> diff --git a/configs/cortina_presidio-asic-base_defconfig b/configs/cortina_presidio-asic-base_defconfig
> new file mode 100644
> index 0000000..45b911c
> --- /dev/null
> +++ b/configs/cortina_presidio-asic-base_defconfig
> @@ -0,0 +1,45 @@
> +# Cortina-Access Ltd. Presidio ASIC Board

This file is re-generated frequently.  Please use 'savedefconfig' on
this next and use that version.

> diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h
> new file mode 100644
> index 0000000..22679ca
> --- /dev/null
> +++ b/include/configs/presidio_asic.h
> @@ -0,0 +1,114 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2020 Cortina Access Inc.
> + *
> + * Configuration for Cortina-Access Presidio board.
> + */
> +
> +#ifndef __PRESIDIO_ASIC_H
> +#define __PRESIDIO_ASIC_H
> +
> +#define CONFIG_REMAKE_ELF
> +
> +#define CONFIG_GICV2
> +
> +#define CONFIG_SUPPORT_RAW_INITRD
> +#define CONFIG_ARMV8_MULTIENTRY
> +
> +/* SMP jump address in DRAM */
> +#define CPU_RELEASE_ADDR		0x0740fff8

non-CONFIG symbols need to be in other header files, not this one.

> +
> +#define CONFIG_SYS_INIT_SP_ADDR		0x00100000
> +#define CONFIG_SYS_BOOTM_LEN		0x00c00000
> +
> +/* Generic Timer Definitions */
> +#define COUNTER_FREQUENCY		25000000
> +#define CONFIG_SYS_TIMER_RATE COUNTER_FREQUENCY
> +#define CONFIG_SYS_TIMER_COUNTER 0xf4321008
> +
> +/* Generic Interrupt Controller Definitions */
> +#define GICD_BASE			0xf7011000
> +#define GICC_BASE			0xf7012000
> +
> +#define CONFIG_SYS_MEMTEST_SCRATCH	0x00100000
> +#define CONFIG_SYS_MEMTEST_START	0x05000000
> +#define CONFIG_SYS_MEMTEST_END		0x0D000000
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (8 << 20))
> +
> +#define CONFIG_SYS_TIMER_BASE		0xf4321000
> +
> +/* Use external clock source */
> +#define PRESIDIO_APB_CLK		125000000
> +#define CORTINA_PER_IO_FREQ		PRESIDIO_APB_CLK
> +
> +/* Cortina Serial Configuration */
> +#define CORTINA_UART_CLOCK		(PRESIDIO_APB_CLK)
> +#define CORTINA_SERIAL_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
> +					 (void *)CONFIG_SYS_SERIAL1}
> +
> +#define CONFIG_BAUDRATE			115200
> +#define CONFIG_SYS_SERIAL0		PER_UART0_CFG
> +#define CONFIG_SYS_SERIAL1		PER_UART1_CFG
> +
> +/* BLOCK Reset Definitions */
> +#define RESET_OTPROM			BIT(29)
> +#define RESET_SD			BIT(28)
> +#define RESET_EAXI			BIT(27)
> +#define RESET_FBM			BIT(26)
> +#define RESET_LDMA			BIT(25)
> +#define RESET_RCRYPTO			BIT(24)
> +#define RESET_SADB			BIT(22)
> +#define RESET_RCPU1			BIT(21)
> +#define RESET_RCPU0			BIT(20)
> +#define RESET_PE1			BIT(19)
> +#define RESET_PE0			BIT(18)
> +#define RESET_RTC			BIT(17)
> +#define RESET_DMA			BIT(16)
> +#define RESET_PER			BIT(15)
> +#define RESET_FLASH			BIT(14)
> +#define RESET_GIC400			BIT(10)
> +#define RESET_SATA			BIT(9)
> +#define RESET_PCIE2			BIT(8)
> +#define RESET_PCIE1			BIT(7)
> +#define RESET_PCIE0			BIT(6)
> +#define RESET_TQM			BIT(5)
> +#define RESET_SDRAM			BIT(4)
> +#define RESET_L3FE			BIT(3)
> +#define RESET_L2TM			BIT(2)
> +#define RESET_L2FE			BIT(1)
> +#define RESET_NI			BIT(0)
> +
> +/* BOOTP options */
> +#define CONFIG_BOOTP_BOOTFILESIZE
> +
> +/* Miscellaneous configurable options */
> +#define DDR_BASE			0x00000000
> +#define CONFIG_SYS_LOAD_ADDR		(DDR_BASE + 0x10000000)
> +#define CONFIG_LAST_STAGE_INIT
> +
> +/* Physical Memory Map */
> +
> +/* SDRAM Bank #1 */
> +#define PHYS_SDRAM_1			DDR_BASE
> +#define PHYS_SDRAM_1_SIZE		0x80000000 /* 2GB */
> +#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
> +
> +/* Initial environment variables */
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS	"silent=y\0"
> +#define CONFIG_BOOTARGS			"earlycon=serial,0xf4329148 console=ttyS0,115200 root=/dev/ram0"

Note that BOOTARGS belongs in the defconfig file.

Thanks!

-- 
Tom
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