[PATCH v2 7/7] doc: board: Add Microchip MPFS Icicle Kit doc

[Padmarao Begari]

On Sat, Oct 24, 2020 at 9:07 PM Jagan Teki <jagan at amarulasolutions.com>
wrote:

> On Thu, Oct 22, 2020 at 1:22 PM Padmarao Begari
> <padmarao.begari at microchip.com> wrote:
> >
> > This doc describes the procedure to build, flash and
> > boot Linux using U-boot on Microchip MPFS Icicle Kit.
> >
> > Signed-off-by: Padmarao Begari <padmarao.begari at microchip.com>
> > ---
> >  doc/board/index.rst                 |   1 +
> >  doc/board/microchip/index.rst       |   9 +
> >  doc/board/microchip/mpfs_icicle.rst | 605 ++++++++++++++++++++++++++++
> >  3 files changed, 615 insertions(+)
> >  create mode 100644 doc/board/microchip/index.rst
> >  create mode 100644 doc/board/microchip/mpfs_icicle.rst
> >
> > diff --git a/doc/board/index.rst b/doc/board/index.rst
> > index 63935abcd7..e50a78d752 100644
> > --- a/doc/board/index.rst
> > +++ b/doc/board/index.rst
> > @@ -15,6 +15,7 @@ Board-specific doc
> >     freescale/index
> >     google/index
> >     intel/index
> > +   microchip/index
> >     renesas/index
> >     rockchip/index
> >     sifive/index
> > diff --git a/doc/board/microchip/index.rst
> b/doc/board/microchip/index.rst
> > new file mode 100644
> > index 0000000000..b09e6788af
> > --- /dev/null
> > +++ b/doc/board/microchip/index.rst
> > @@ -0,0 +1,9 @@
> > +.. SPDX-License-Identifier: GPL-2.0+
> > +
> > +Microchip
> > +======
> > +
> > +.. toctree::
> > +   :maxdepth: 2
> > +
> > +   mpfs_icicle
> > diff --git a/doc/board/microchip/mpfs_icicle.rst
> b/doc/board/microchip/mpfs_icicle.rst
> > new file mode 100644
> > index 0000000000..a4876b02f7
> > --- /dev/null
> > +++ b/doc/board/microchip/mpfs_icicle.rst
> > @@ -0,0 +1,605 @@
> > +.. SPDX-License-Identifier: GPL-2.0+
> > +
> > +Microchip PolarFire SoC Icicle Kit
> > +==================================
> > +
> > +RISC-V PolarFire SoC
> > +---------------------
> > +The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip.
> > +
> > +The Icicle Kit development platform is based on PolarFire SoC and
> capable
> > +of running Linux.
> > +
> > +Mainline support
> > +----------------
> > +The support for following drivers are already enabled:
> > +
> > +1. NS16550 UART Driver.
> > +2. Microchip Clock Driver.
> > +3. Cadence MACB ethernet driver for networking support.
> > +4. Cadence MMC Driver for eMMC/SD support.
> > +
> > +Booting from eMMC using HSS
> > +---------------------------
> > +
> > +Building
> > +--------
> > +
> > +1. Add the RISC-V toolchain to your PATH.
> > +2. Setup ARCH & cross compilation environment variable:
> > +
> > +.. code-block:: none
> > +
> > +   export CROSS_COMPILE=<riscv64 toolchain prefix>
> > +
> > +3. make microchip_mpfs_icicle_defconfig
> > +4. make
> > +
> > +Flashing
> > +--------
> > +
> > +The current U-Boot port is supported in S-mode only and loaded from
> DRAM.
> > +
> > +A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is
> required to
> > +boot the u-boot.bin in S-mode.
> > +
> > +Currently, the u-boot.bin is used as a payload of the HSS firmware.
> > +
> > +You will be creating a payload from `u-boot-dtb.bin`.
> > +Copy this file to the toplevel HSS (Hart Software Services) directory.
>
> It might be a strange question, but in order to support standardized
> bootflow with SPL
>
> I think the DRAM initialization is part of HSS, can we able to build
> move that DRAM init part out of HSS? If so we can have SPL that loads
> HSS. This might be a strange question but it would be a final goal in
> order to standardize bootflow like other RISC-V targets in Mainline.
>
>
U-Boot SPL is our future plan. Presently we are going with the Microchip
boot-flow and custom boot-flow.

Regards
Padmarao

> Jagan.
>