[PATCH v5 1/2] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Biju Das]

Hi Marek,


> On 11/3/20 11:06 AM, Biju Das wrote:
> > Hi Marek,
> 
> Hi,
> 
> [...]
> 
> >>> On the next version, I will send Renesas SoC identification driver,
> >>> which supports caching family type which can be used to provide
> >>> unique
> >> identification for CPU type.
> >>
> >> Please make sure to check it on RCar2 as well, those use SPL and the
> >> SPL size is quite limited.
> >
> > Currently SoC identification driver is enabled only for RZ/G2 boards and
> support is added to both R-Car Gen3 and RZ/G2 devices.
> >
> > For the disabled case, the UCLASS-SOC class functions are inlined to "NULL"
> for soc_device_match and rest of the api's it is "-ENOSYS".
> >
> > I agree, in future we need to add support for RCar2 as well, since we are
> going to add u-boot support for RZ/G1 devices.
> > Please find the size details related to R-Car Gen2(by adding support for R-
> Car M2-W and RZ/G1M SoC).
> >
> > There is increase of 944 bytes, for R-Car Gen2 device, if we enable Renesas
> SoC identification driver for Gen2 devices.
> >
> > Current u-boot-sh/master
> > -----------------------------------
> > $ ls -al u-boot.bin
> > -rw-r--r-- 1 biju biju 523001 Nov  3 09:16 u-boot.bin
> >
> > Current u-boot-sh/master + SoC renesas driver (R-Car M2-W enabled only
> > case)
> > ----------------------------------------------------------------------
> > ----------------------
> > $ ls -al u-boot.bin
> > -rw-r--r-- 1 biju biju 523945 Nov  3 09:47 u-boot.bin
> >
> > If you agree, we will add support for Gen2 to SoC identification driver later.
> Currently there is no users for using it.
> > Please let me know.
> 
> The problem on Gen2 isn't the size of u-boot.bin , but of spl/u-boot-spl.bin .
> That one is severely limited and I don't think it's realistic to add any sort of
> SoC identification driver into it. In fact, I think even the DM is somehow
> reduced in there.

Yes, I agree there is size constraint for Gen2 for spl/u-boot-spl.bin. Even in Gen3, we don't compile core/pinctrl driver for SPL.
See, from drivers/Makefile. 

obj-$(CONFIG_$(SPL_TPL_)DM)
obj-$(CONFIG_$(SPL_TPL_)PINCTRL) += pinctrl/

if we enable this, then we get linker error related to region .sram overflow messages.

Please let me know, shall I post a patch series with SoC Identification and SDHI quirks or still have some open points?

Regards,
Biju