[RESEND,PATCH v2 0/1] RISC-V tracing support

[Pragnesh Patel]

This series add a support of tracing for RISC-V arch.

This series is also available here [1] for testing.
[1] https://github.com/pragnesh26992/u-boot/tree/trace

How to test this patch:
1) Enable tracing in "configs/sifive_fu540_defconfig"
CONFIG_TRACE=y
CONFIG_TRACE_BUFFER_SIZE=0x01000000
CONFIG_TRACE_CALL_DEPTH_LIMIT=15
CONFIG_CMD_TRACE=y

2) make FTRACE=1 sifive_fu540_defconfig
3) make FTRACE=1

Following are the boot messages on FU540 five cores SMP platform:

U-Boot SPL 2021.01-rc1-00244-gc0ac5b69ea-dirty (Nov 05 2020 - 15:21:06 +0530)
Trying to boot from MMC1


U-Boot 2021.01-rc1-00244-gc0ac5b69ea-dirty (Nov 05 2020 - 15:21:06 +0530)

CPU:   rv64imafdc
Model: SiFive HiFive Unleashed A00
DRAM:  8 GiB
trace: enabled
MMC:   spi at 10050000:mmc at 0: 0
*** Warning - bad CRC, using default environment

In:    serial at 10010000
Out:   serial at 10010000
Err:   serial at 10010000
Board serial number should not be 0 !!
Net:
Error: ethernet at 10090000 address not set.
No ethernet found.

Hit any key to stop autoboot:  0
=> trace stats
        178,556 function sites
      9,378,800 function calls
              1 untracked function calls
      1,279,056 traced function calls (8070507 dropped due to overflow)
             19 maximum observed call depth
             15 call depth limit
      9,568,845 calls not traced due to depth
=> trace calls 0x83000000 0xf00000
Call list dumped to 83000000, size 0xea33d0
=>


Pragnesh Patel (1):
  riscv: Add timer_get_us() for tracing

 drivers/timer/andes_plmt_timer.c   | 16 +++++++++++++++-
 drivers/timer/riscv_timer.c        | 14 +++++++++++++-
 drivers/timer/sifive_clint_timer.c | 16 +++++++++++++++-
 3 files changed, 43 insertions(+), 3 deletions(-)

-- 
2.17.1